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Clifford Wolf 2014-02-06 14:01:43 +01:00
parent c13c5b9b7b
commit 821156b6cf
10 changed files with 265 additions and 12 deletions
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15
manual/PRESENTATION_ExAdv/select_01.v Normal file
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module test(clk, s, a, y);
input clk, s;
input [15:0] a;
output [15:0] y;
reg [15:0] b, c;
always @(posedge clk) begin
b <= a;
c <= b;
end
wire [15:0] state_a = (a ^ b) + c;
wire [15:0] state_b = (a ^ b) - c;
assign y = !s ? state_a : state_b;
endmodule