presentation progress

manual/PRESENTATION_ExAdv/.gitignore

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+*.dot

manual/PRESENTATION_ExAdv/Makefile

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+
+all: select_01.pdf
+
+select_01.pdf: select_01.v select_01.ys
+	../../yosys select_01.ys
+

manual/PRESENTATION_ExAdv/select_01.v

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+module test(clk, s, a, y);
+    input clk, s;
+    input [15:0] a;
+    output [15:0] y;
+    reg [15:0] b, c;
+
+    always @(posedge clk) begin
+        b <= a;
+        c <= b;
+    end
+
+    wire [15:0] state_a = (a ^ b) + c;
+    wire [15:0] state_b = (a ^ b) - c;
+    assign y = !s ? state_a : state_b;
+endmodule

manual/PRESENTATION_ExAdv/select_01.ys

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+read_verilog select_01.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select_01 -format pdf -notitle \
+     -color red @cone_ab -color magenta @cone_a \
+     -color blue @cone_b