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added stimulus mode and param check

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This commit is contained in:
Miodrag Milanovic 2022-02-02 09:37:32 +01:00
parent 8ba2000a50
commit 820b2fdd65
1 changed files with 31 additions and 5 deletions
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36
passes/sat/sim.cc
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@ -29,6 +29,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
enum class SimulationMode { enum class SimulationMode {
sim,
cmp, cmp,
gold, gold,
gate, gate,
@ -73,7 +74,7 @@ struct SimShared
FstData *fst = nullptr; FstData *fst = nullptr;
double start_time = 0; double start_time = 0;
double stop_time = -1; double stop_time = -1;
SimulationMode sim_mode = SimulationMode::cmp; SimulationMode sim_mode = SimulationMode::sim;
bool cycles_set = false; bool cycles_set = false;
}; };
@ -746,7 +747,9 @@ struct SimInstance
Const sim_val = get_state(item.first); Const sim_val = get_state(item.first);
if (sim_val.size()!=fst_val.size()) if (sim_val.size()!=fst_val.size())
log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first)); log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X if (shared->sim_mode == SimulationMode::sim) {
// No checks performed when using stimulus
} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) { for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) { if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val)); log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
@ -1109,10 +1112,10 @@ struct SimPass : public Pass {
log(" include the specified timescale declaration in the vcd\n"); log(" include the specified timescale declaration in the vcd\n");
log("\n"); log("\n");
log(" -n <integer>\n"); log(" -n <integer>\n");
log(" number of cycles to simulate (default: 20)\n"); log(" number of clock cycles to simulate (default: 20)\n");
log("\n"); log("\n");
log(" -a\n"); log(" -a\n");
log(" include all nets in VCD output, not just those with public names\n"); log(" use all nets in VCD/FST operations, not just those with public names\n");
log("\n"); log("\n");
log(" -w\n"); log(" -w\n");
log(" writeback mode: use final simulation state as new init state\n"); log(" writeback mode: use final simulation state as new init state\n");
@ -1123,14 +1126,20 @@ struct SimPass : public Pass {
log(" -scope\n"); log(" -scope\n");
log(" scope of simulation top model\n"); log(" scope of simulation top model\n");
log("\n"); log("\n");
log(" -at <time>\n");
log(" sets start and stop time\n");
log("\n");
log(" -start <time>\n"); log(" -start <time>\n");
log(" start co-simulation in arbitary time (default 0)\n"); log(" start co-simulation in arbitary time (default 0)\n");
log("\n"); log("\n");
log(" -stop <time>\n"); log(" -stop <time>\n");
log(" stop co-simulation in arbitary time (default END)\n"); log(" stop co-simulation in arbitary time (default END)\n");
log("\n"); log("\n");
log(" -sim\n");
log(" simulation with stimulus from FST (default)\n");
log("\n");
log(" -sim-cmp\n"); log(" -sim-cmp\n");
log(" co-simulation expect exact match (default)\n"); log(" co-simulation expect exact match\n");
log("\n"); log("\n");
log(" -sim-gold\n"); log(" -sim-gold\n");
log(" co-simulation, x in simulation can match any value in FST\n"); log(" co-simulation, x in simulation can match any value in FST\n");
@ -1146,6 +1155,7 @@ struct SimPass : public Pass {
{ {
SimWorker worker; SimWorker worker;
int numcycles = 20; int numcycles = 20;
bool start_set = false, stop_set = false, at_set = false;
log_header(design, "Executing SIM pass (simulate the circuit).\n"); log_header(design, "Executing SIM pass (simulate the circuit).\n");
@ -1220,10 +1230,22 @@ struct SimPass : public Pass {
} }
if (args[argidx] == "-start" && argidx+1 < args.size()) { if (args[argidx] == "-start" && argidx+1 < args.size()) {
worker.start_time = stringToTime(args[++argidx]); worker.start_time = stringToTime(args[++argidx]);
start_set = true;
continue; continue;
} }
if (args[argidx] == "-stop" && argidx+1 < args.size()) { if (args[argidx] == "-stop" && argidx+1 < args.size()) {
worker.stop_time = stringToTime(args[++argidx]); worker.stop_time = stringToTime(args[++argidx]);
stop_set = true;
continue;
}
if (args[argidx] == "-at" && argidx+1 < args.size()) {
worker.start_time = stringToTime(args[++argidx]);
worker.stop_time = worker.start_time;
at_set = true;
continue;
}
if (args[argidx] == "-sim") {
worker.sim_mode = SimulationMode::sim;
continue; continue;
} }
if (args[argidx] == "-sim-cmp") { if (args[argidx] == "-sim-cmp") {
@ -1241,6 +1263,10 @@ struct SimPass : public Pass {
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (at_set && (start_set || stop_set || worker.cycles_set))
log_error("'at' option can only be defined separate of 'start','stop' and 'n'\n");
if (stop_set && worker.cycles_set)
log_error("'stop' and 'n' can only be used exclusively'\n");
Module *top_mod = nullptr; Module *top_mod = nullptr;