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Revert "Add groups to command reference"

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N. Engelhardt 2025-07-23 14:41:49 +00:00 • committed by GitHub
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docs/source/yosys_internals/verilog.rst
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@ -96,7 +96,7 @@ Verilog Attributes and non-standard features
- The ``keep_hierarchy`` attribute on cells and modules keeps the `flatten`
command from flattening the indicated cells and modules.
- The ``gate_cost_equivalent`` attribute on a module can be used to specify
- The `gate_cost_equivalent` attribute on a module can be used to specify
the estimated cost of the module as a number of basic gate instances. See
the help message of command `keep_hierarchy` which interprets this
attribute.