Revert "Add groups to command reference"

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -323,10 +323,10 @@ tools).
   design into an equivalent design that is easier to analyse.
 - Commands such as `eval` and `sat` can be used to investigate the behavior of
   the circuit.
-- :cmd:title:`show`.
-- :cmd:title:`dump`.
-- :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
-  a design dynamically.
+- :doc:`/cmd/show`.
+- :doc:`/cmd/dump`.
+- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
+  design dynamically.
   
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
@@ -358,7 +358,7 @@ reorganizing a module in Yosys and checking the resulting circuit.
 .. figure:: /_images/code_examples/scrambler/scrambler_p02.*
     :class: width-helper invert-helper
 
-Analyzing the resulting circuit with :cmd:title:`eval`:
+Analyzing the resulting circuit with :doc:`/cmd/eval`:
 
 .. todo:: replace inline code
 

docs/source/using_yosys/more_scripting/load_design.rst

@@ -1,11 +1,9 @@
 Loading a design
 ~~~~~~~~~~~~~~~~
 
-.. TODO:: fill out this page better
-
 keyword: Frontends
 
-- :doc:`/cmd/index_frontends`
+- :doc:`/cmd/read_verilog`
 
 .. todo:: include ``read_verilog <<EOF``, also other methods of loading designs
 
@@ -31,14 +29,20 @@ keyword: Frontends
 
 .. note::
 
-   The Verific frontend for Yosys, which provides the `verific` command,
-   requires Yosys to be built with Verific.  For full functionality, custom
-   modifications to the Verific source code from YosysHQ are required, but
-   limited useability can be achieved with some stock Verific builds.  Check
+   The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
+   command, requires Yosys to be built with Verific.  For full functionality,
+   custom modifications to the Verific source code from YosysHQ are required,
+   but limited useability can be achieved with some stock Verific builds.  Check
    :doc:`/yosys_internals/extending_yosys/build_verific` for more.
 
 Others:
 
+- :doc:`/cmd/read`
 - `GHDL plugin`_ for VHDL
+- :doc:`/cmd/read_rtlil` (direct textual representation of Yosys internal state)
+- :doc:`/cmd/read_aiger`
+- :doc:`/cmd/read_blif`
+- :doc:`/cmd/read_json`
+- :doc:`/cmd/read_liberty`
 
 .. _GHDL plugin: https://github.com/ghdl/ghdl-yosys-plugin

docs/source/using_yosys/more_scripting/selections.rst

@@ -93,7 +93,7 @@ Special patterns can be used to select by object property or type. For example:
   A:blabla`
 - select all `$add` cells from the module foo: :yoscrypt:`select foo/t:$add`
 
-A complete list of pattern expressions can be found in :cmd:title:`select`.
+A complete list of pattern expressions can be found in :doc:`/cmd/select`.
 
 Operations on selections
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -141,7 +141,7 @@ Some of the special ``%``-codes:
 - ``%i``: intersection of top two elements on stack -- pop 2, push 1
 - ``%n``: inverse of top element on stack -- pop 1, push 1
 
-See :cmd:title:`select` for the full list.
+See :doc:`/cmd/select` for the full list.
 
 Expanding selections
 ^^^^^^^^^^^^^^^^^^^^
@@ -354,7 +354,7 @@ boolean operations such as intersection (``%i``) and difference (``%d``) are
 powerful tools for extracting the relevant portions of the circuit under
 investigation.
 
-Again, see :cmd:title:`select` for full documentation of these expressions.
+Again, see :doc:`/cmd/select` for full documentation of these expressions.
 
 Incremental selection
 ^^^^^^^^^^^^^^^^^^^^^