Revert "Add groups to command reference"

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -323,10 +323,10 @@ tools).
   design into an equivalent design that is easier to analyse.
 - Commands such as `eval` and `sat` can be used to investigate the behavior of
   the circuit.
-- :cmd:title:`show`.
-- :cmd:title:`dump`.
-- :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
-  a design dynamically.
+- :doc:`/cmd/show`.
+- :doc:`/cmd/dump`.
+- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
+  design dynamically.
   
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
@@ -358,7 +358,7 @@ reorganizing a module in Yosys and checking the resulting circuit.
 .. figure:: /_images/code_examples/scrambler/scrambler_p02.*
     :class: width-helper invert-helper
 
-Analyzing the resulting circuit with :cmd:title:`eval`:
+Analyzing the resulting circuit with :doc:`/cmd/eval`:
 
 .. todo:: replace inline code
 

docs/source/using_yosys/more_scripting/load_design.rst

@@ -1,11 +1,9 @@
 Loading a design
 ~~~~~~~~~~~~~~~~
 
-.. TODO:: fill out this page better
-
 keyword: Frontends
 
-- :doc:`/cmd/index_frontends`
+- :doc:`/cmd/read_verilog`
 
 .. todo:: include ``read_verilog <<EOF``, also other methods of loading designs
 
@@ -31,14 +29,20 @@ keyword: Frontends
 
 .. note::
 
-   The Verific frontend for Yosys, which provides the `verific` command,
-   requires Yosys to be built with Verific.  For full functionality, custom
-   modifications to the Verific source code from YosysHQ are required, but
-   limited useability can be achieved with some stock Verific builds.  Check
+   The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
+   command, requires Yosys to be built with Verific.  For full functionality,
+   custom modifications to the Verific source code from YosysHQ are required,
+   but limited useability can be achieved with some stock Verific builds.  Check
    :doc:`/yosys_internals/extending_yosys/build_verific` for more.
 
 Others:
 
+- :doc:`/cmd/read`
 - `GHDL plugin`_ for VHDL
+- :doc:`/cmd/read_rtlil` (direct textual representation of Yosys internal state)
+- :doc:`/cmd/read_aiger`
+- :doc:`/cmd/read_blif`
+- :doc:`/cmd/read_json`
+- :doc:`/cmd/read_liberty`
 
 .. _GHDL plugin: https://github.com/ghdl/ghdl-yosys-plugin

docs/source/using_yosys/more_scripting/selections.rst

@@ -93,7 +93,7 @@ Special patterns can be used to select by object property or type. For example:
   A:blabla`
 - select all `$add` cells from the module foo: :yoscrypt:`select foo/t:$add`
 
-A complete list of pattern expressions can be found in :cmd:title:`select`.
+A complete list of pattern expressions can be found in :doc:`/cmd/select`.
 
 Operations on selections
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -141,7 +141,7 @@ Some of the special ``%``-codes:
 - ``%i``: intersection of top two elements on stack -- pop 2, push 1
 - ``%n``: inverse of top element on stack -- pop 1, push 1
 
-See :cmd:title:`select` for the full list.
+See :doc:`/cmd/select` for the full list.
 
 Expanding selections
 ^^^^^^^^^^^^^^^^^^^^
@@ -354,7 +354,7 @@ boolean operations such as intersection (``%i``) and difference (``%d``) are
 powerful tools for extracting the relevant portions of the circuit under
 investigation.
 
-Again, see :cmd:title:`select` for full documentation of these expressions.
+Again, see :doc:`/cmd/select` for full documentation of these expressions.
 
 Incremental selection
 ^^^^^^^^^^^^^^^^^^^^^

docs/source/using_yosys/synthesis/fsm.rst

@@ -10,7 +10,7 @@ other commands:
    :start-after: #end:
    :caption: Passes called by `fsm`
 
-See also :doc:`/cmd/index_passes_fsm`.
+See also :doc:`/cmd/fsm`.
 
 The algorithms used for FSM detection and extraction are influenced by a more
 general reported technique :cite:p:`fsmextract`.

docs/source/using_yosys/synthesis/memory.rst

@@ -26,7 +26,7 @@ Some quick notes:
    decoder logic and registers.
 
 For more information about `memory`, such as disabling certain sub commands, see
-:doc:`/cmd/index_passes_memory`.
+:doc:`/cmd/memory`.
 
 Example
 -------

docs/source/using_yosys/synthesis/opt.rst

@@ -11,8 +11,8 @@ The `opt` macro command
 
 The Yosys pass `opt` runs a number of simple optimizations. This includes
 removing unused signals and cells and const folding. It is recommended to run
-this pass after each major step in the synthesis script.  This macro command
-calls the following ``opt_*`` commands:
+this pass after each major step in the synthesis script.  As listed in
+:doc:`/cmd/opt`, this macro command calls the following ``opt_*`` commands:
 
 .. literalinclude:: /code_examples/macro_commands/opt.ys
    :language: yoscrypt
@@ -233,5 +233,7 @@ Other optimizations
 
 .. todo:: more on the other optimizations
 
-- Check :doc:`/cmd/index_passes_opt` for more.
+- :doc:`/cmd/wreduce`
+- :doc:`/cmd/peepopt`
+- :doc:`/cmd/share`
 - `abc` and `abc9`, see also: :doc:`abc`.

docs/source/using_yosys/synthesis/proc.rst

@@ -17,7 +17,7 @@ commands in a sensible order:
 
 After all the ``proc_*`` commands, `opt_expr` is called. This can be disabled by
 calling :yoscrypt:`proc -noopt`.  For more information about `proc`, such as
-disabling certain sub commands, see :doc:`/cmd/index_passes_proc`.
+disabling certain sub commands, see :doc:`/cmd/proc`.
 
 Many commands can not operate on modules with "processess" in them. Usually a
 call to `proc` is the first command in the actual synthesis procedure after

docs/source/using_yosys/synthesis/synth.rst

@@ -6,23 +6,44 @@ Synth commands
 Packaged ``synth_*`` commands
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-A list of all synth commands included in Yosys for different platforms can be
-found under :doc:`/cmd/index_techlibs`.  Each command runs a script of sub
-commands specific to the platform being targeted.  Note that not all of these
-scripts are actively maintained and may not be up-to-date.
+The following is a list of all synth commands included in Yosys for different
+platforms.  Each command runs a script of sub commands specific to the platform
+being targeted.  Note that not all of these scripts are actively maintained and
+may not be up-to-date.
+
+- :doc:`/cmd/synth_achronix`
+- :doc:`/cmd/synth_anlogic`
+- :doc:`/cmd/synth_coolrunner2`
+- :doc:`/cmd/synth_easic`
+- :doc:`/cmd/synth_ecp5`
+- :doc:`/cmd/synth_efinix`
+- :doc:`/cmd/synth_fabulous`
+- :doc:`/cmd/synth_gatemate`
+- :doc:`/cmd/synth_gowin`
+- :doc:`/cmd/synth_greenpak4`
+- :doc:`/cmd/synth_ice40`
+- :doc:`/cmd/synth_intel` (MAX10, Cyclone IV)
+- :doc:`/cmd/synth_intel_alm` (Cyclone V, Arria V, Cyclone 10 GX)
+- :doc:`/cmd/synth_lattice`
+- :doc:`/cmd/synth_nexus`
+- :doc:`/cmd/synth_quicklogic`
+- :doc:`/cmd/synth_sf2`
+- :doc:`/cmd/synth_xilinx`
 
 General synthesis
 ~~~~~~~~~~~~~~~~~
 
 In addition to the above hardware-specific synth commands, there is also
-:cmd:title:`prep`.  This command is limited to coarse-grain synthesis, without
+:doc:`/cmd/prep`.  This command is limited to coarse-grain synthesis, without
 getting into any architecture-specific mappings or optimizations.  Among other
 things, this is useful for design verification.
 
 The following commands are executed by the `prep` command:
 
-.. literalinclude:: /code_examples/macro_commands/prep.ys
+.. literalinclude:: /cmd/prep.rst
    :start-at: begin:
+   :end-before: .. only:: latex
+   :dedent:
 
 :doc:`/getting_started/example_synth` covers most of these commands and what
 they do.

docs/source/using_yosys/synthesis/techmap_synth.rst

@@ -33,9 +33,9 @@ reader may find this map file as :file:`techlibs/common/techmap.v` in the Yosys
 source tree.
 
 Additional features have been added to techmap to allow for conditional mapping
-of cells (see :doc:`/cmd/index_passes_techmap`). This can for example be useful
-if the target architecture supports hardware multipliers for certain bit-widths
-but not for others.
+of cells (see :doc:`/cmd/techmap`). This can for example be useful if the target
+architecture supports hardware multipliers for certain bit-widths but not for
+others.
 
 A usual synthesis flow would first use the techmap pass to directly map some RTL
 cells to coarse-grain cells provided by the target architecture (if any) and