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cells can now be created, techmap broken

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This commit is contained in:
Emil J. Tywoniak 2024-06-18 19:16:48 +02:00
parent b190055bbb
commit 81f783bf62
3 changed files with 19 additions and 49 deletions
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4
passes/tests/test_cell.cc
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@ -41,10 +41,6 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
{
RTLIL::Module *module = design->addModule(ID(gold));
RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
for (auto para : cell->parameters)
log("param %s is %s\n", para.first.c_str(), para.second.as_string().c_str());
// for (auto para : cell->connections)
// log("param %s is %s\n", para.first.c_str(), para.second.as_string());
RTLIL::Wire *wire;
if (cell_type.in(ID($mux), ID($pmux)))