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Add check at constmap and merge test

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This commit is contained in:
Kelvin Chung 2025-04-14 11:44:52 +01:00
parent 414dc85573
commit 81f3369f24
2 changed files with 31 additions and 27 deletions
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22
tests/techmap/constmap.ys
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@ -9,8 +9,7 @@ endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell
select -assert-count 1 r:value=16
select -assert-count 1 t:const_cell r:value=16 %i
design -reset
@ -42,22 +41,3 @@ select -assert-count 1 test/out1 %ci* r:value=16 %i
select -assert-count 1 test/out2 %ci* r:value=32 %i
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i
design -reset
read_verilog << EOT
module test();
wire [31:0] in;
wire [31:0] out1;
wire [31:0] out2;
assign out1 = in + 16;
assign out2 = in + 32;
endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i