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ast, read_verilog: unify location types, reduce filename copying
This commit is contained in:
Emil J. Tywoniak
parent
b276fb6616
commit
81e5270484
12 changed files with 715 additions and 693 deletions
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@ -45,7 +45,7 @@ using namespace AST_INTERNAL;
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// helper function for creating RTLIL code for unary operations
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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return;
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}
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
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set_src_attr(cell, that);
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@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -138,7 +138,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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log_assert(cond.size() == 1);
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std::stringstream sstr;
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sstr << "$ternary$" << RTLIL::encode_filename(that->location.filename) << ":" << that->location.first_line << "$" << (autoidx++);
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sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
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set_src_attr(cell, that);
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@ -195,12 +195,12 @@ struct AST_INTERNAL::LookaheadRewriter
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if (node->lookahead) {
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log_assert(node->type == AST_IDENTIFIER);
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if (!lookaheadids.count(node->str)) {
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auto wire = std::make_unique<AstNode>(AST_WIRE);
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auto wire = std::make_unique<AstNode>(node->location, AST_WIRE);
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for (auto& c : node->id2ast->children)
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wire->children.push_back(c->clone());
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wire->fixup_hierarchy_flags();
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wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(node->location, 1, false));
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wire->is_logic = true;
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while (wire->simplify(true, 1, -1, false)) { }
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lookaheadids[node->str] = make_pair(node->id2ast, wire.get());
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@ -271,6 +271,7 @@ struct AST_INTERNAL::LookaheadRewriter
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// top->dumpVlog(nullptr, "REWRITE-BEFORE> ");
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AstNode *block = nullptr;
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auto loc = top->location;
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for (auto& c : top->children)
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if (c->type == AST_BLOCK) {
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@ -284,18 +285,18 @@ struct AST_INTERNAL::LookaheadRewriter
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for (auto it : lookaheadids)
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{
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auto ref_orig = std::make_unique<AstNode>(AST_IDENTIFIER);
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auto ref_orig = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
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ref_orig->str = it.second.first->str;
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ref_orig->id2ast = it.second.first;
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ref_orig->was_checked = true;
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auto ref_temp = std::make_unique<AstNode>(AST_IDENTIFIER);
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auto ref_temp = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
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ref_temp->str = it.second.second->str;
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ref_temp->id2ast = it.second.second;
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ref_temp->was_checked = true;
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auto init_assign = std::make_unique<AstNode>(AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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auto final_assign = std::make_unique<AstNode>(AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
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auto init_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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auto final_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
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block->children.insert(block->children.begin(), std::move(init_assign));
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block->children.push_back(std::move(final_assign));
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@ -347,7 +348,7 @@ struct AST_INTERNAL::ProcessGenerator
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LookaheadRewriter la_rewriter(always.get());
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// generate process and simple root case
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->location.filename).c_str(), always->location.first_line, autoidx++));
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename).c_str(), always->location.begin.line, autoidx++));
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set_src_attr(proc, always.get());
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -723,7 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
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if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" ||
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ast->str == "$write" || ast->str == "$writeb" || ast->str == "$writeh" || ast->str == "$writeo") {
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std::stringstream sstr;
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sstr << ast->str << "$" << ast->location.filename << ":" << ast->location.first_line << "$" << (autoidx++);
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sstr << ast->str << "$" << ast->location.begin.filename << ":" << ast->location.begin.line << "$" << (autoidx++);
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Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
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set_src_attr(en, ast);
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@ -766,8 +767,8 @@ struct AST_INTERNAL::ProcessGenerator
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node->detectSignWidth(width, is_signed, nullptr);
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VerilogFmtArg arg = {};
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arg.filename = node->location.filename;
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arg.first_line = node->location.first_line;
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arg.filename = *node->location.begin.filename;
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arg.first_line = node->location.begin.line;
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if (node->type == AST_CONSTANT && node->is_string) {
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arg.type = VerilogFmtArg::STRING;
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arg.str = node->bitsAsConst().decode_string();
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@ -793,7 +794,7 @@ struct AST_INTERNAL::ProcessGenerator
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fmt.append_literal("\n");
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fmt.emit_rtlil(cell);
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} else if (!ast->str.empty()) {
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log_file_error(ast->location.filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
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log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
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}
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break;
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@ -813,7 +814,7 @@ struct AST_INTERNAL::ProcessGenerator
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IdString cellname;
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if (ast->str.empty())
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(ast->location.filename).c_str(), ast->location.first_line, autoidx++);
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*ast->location.begin.filename).c_str(), ast->location.begin.line, autoidx++);
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else
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cellname = ast->str;
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check_unique_id(current_module, cellname, ast, "procedural assertion");
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@ -843,7 +844,7 @@ struct AST_INTERNAL::ProcessGenerator
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set_src_attr(cell, ast);
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(ast->location.filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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cell->setParam(ID::FLAVOR, flavor);
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@ -1503,7 +1504,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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RTLIL::SigSpec sig = realAsConst(width_hint);
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log_file_warning(location.filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
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log_file_warning(*location.begin.filename, location.begin.line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
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return sig;
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}
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@ -1535,7 +1536,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (dynamic_cast<RTLIL::Binding*>(current_module)) {
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/* nothing to do here */
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} else if (flag_autowire)
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log_file_warning(location.filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
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log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str());
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else
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input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
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}
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@ -1610,7 +1611,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
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input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
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int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
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auto fake_ast = std::make_unique<AstNode>(AST_NONE, clone(), children[0]->children.size() >= 2 ?
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auto fake_ast = std::make_unique<AstNode>(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ?
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children[0]->children[1]->clone() : children[0]->children[0]->clone());
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fake_ast->children[0]->delete_children();
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if (member_node)
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@ -1640,10 +1641,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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chunk.offset = source_width - (chunk.offset + chunk.width);
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if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) {
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if (chunk.width == 1)
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log_file_warning(location.filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
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log_file_warning(*location.begin.filename, location.begin.line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
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str.c_str());
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else
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log_file_warning(location.filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
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log_file_warning(*location.begin.filename, location.begin.line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
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children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
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chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
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} else {
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@ -1657,10 +1658,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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chunk.offset += add_undef_bits_lsb;
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}
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if (add_undef_bits_lsb)
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log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
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log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
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children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
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if (add_undef_bits_msb)
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log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
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log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
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children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
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}
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}
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@ -1934,7 +1935,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_MEMRD:
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{
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std::stringstream sstr;
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sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
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set_src_attr(cell, this);
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@ -1972,7 +1973,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_MEMINIT:
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{
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std::stringstream sstr;
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sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
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SigSpec en_sig = children[2]->genRTLIL();
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@ -2017,7 +2018,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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IdString cellname;
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if (str.empty())
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(location.filename).c_str(), location.first_line, autoidx++);
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
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else
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cellname = str;
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check_unique_id(current_module, cellname, this, "procedural assertion");
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@ -2060,7 +2061,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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new_left.append(left[i]);
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new_right.append(right[i]);
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}
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log_file_warning(location.filename, location.first_line, "Ignoring assignment to constant bits:\n"
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log_file_warning(*location.begin.filename, location.begin.line, "Ignoring assignment to constant bits:\n"
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" old assignment: %s = %s\n new assignment: %s = %s.\n",
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log_signal(left), log_signal(right),
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log_signal(new_left), log_signal(new_right));
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@ -2095,7 +2096,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
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const AstNode *value = child->children[0].get();
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if (value->type == AST_REALVALUE)
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log_file_warning(location.filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
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log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
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log_id(cell), log_id(paraname), value->realvalue);
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else if (value->type != AST_CONSTANT)
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input_error("Parameter %s.%s with non-constant value!\n",
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@ -2192,14 +2193,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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int sz = children.size();
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if (str == "$info") {
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if (sz > 0)
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log_file_info(location.filename, location.first_line, "%s.\n", children[0]->str.c_str());
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log_file_info(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
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else
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log_file_info(location.filename, location.first_line, "\n");
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log_file_info(*location.begin.filename, location.begin.line, "\n");
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} else if (str == "$warning") {
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if (sz > 0)
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log_file_warning(location.filename, location.first_line, "%s.\n", children[0]->str.c_str());
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log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
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else
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log_file_warning(location.filename, location.first_line, "\n");
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log_file_warning(*location.begin.filename, location.begin.line, "\n");
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} else if (str == "$error") {
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if (sz > 0)
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input_error("%s.\n", children[0]->str.c_str());
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