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	opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
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								tests/opt/opt_expr_xor.ys
									
										
									
									
									
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								tests/opt/opt_expr_xor.ys
									
										
									
									
									
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					read_verilog <<EOT
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					module top(input a, output [3:0] y);
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					assign y[0] = a^1'b0;
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					assign y[1] = 1'b1^a;
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					assign y[2] = a~^1'b0;
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					assign y[3] = 1'b1^~a;
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					endmodule
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					EOT
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					design -save read
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					select -assert-count 2 t:$xor
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					select -assert-count 2 t:$xnor
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					equiv_opt opt_expr
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					design -load postopt
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					select -assert-none t:$xor
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					select -assert-none t:$xnor
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					select -assert-count 2 t:$_NOT_
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					design -load read
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					simplemap
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					equiv_opt opt_expr
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					design -load postopt
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					select -assert-none t:$_XOR_
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					select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
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					select -assert-count 3 t:$_NOT_
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					design -reset
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					read_verilog -icells <<EOT
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					module top(input a, output [1:0] y);
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					$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
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					$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
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					endmodule
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					EOT
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					select -assert-count 2 t:$_XNOR_
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					equiv_opt opt_expr
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					design -load postopt
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					select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
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					select -assert-count 1 t:$_NOT_
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