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Added tests/techmap/mem_simple_4x1

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Clifford Wolf 2014-02-21 12:06:40 +01:00
parent 79f8944811
commit 81b3f52519
8 changed files with 215 additions and 0 deletions
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13
tests/techmap/mem_simple_4x1_cells.v Normal file
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module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
input CLK, WR_DATA, WR_EN;
input [3:0] RD_ADDR, WR_ADDR;
output reg RD_DATA;
reg [15:0] memory;
always @(posedge CLK) begin
if (WR_EN)
memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];
end
endmodule