3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 11:20:27 +00:00

Changes in GoWin synth commands and ALU primitive support

This commit is contained in:
Diego H 2018-12-03 20:08:35 -06:00
parent 47c89d600c
commit 819ca73096
5 changed files with 91 additions and 12 deletions

View file

@ -57,3 +57,9 @@ endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
parameter [3:0] ALU_MODE = 0; // default 0 = ADD
assign {COUT, SUM} = CIN + I1 + I0;
endmodule // alu