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Fix tests for check in equiv_opt

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Jannis Harder 2022-08-25 14:24:31 +02:00
parent 0516307637
commit 81906aa627
13 changed files with 31 additions and 15 deletions
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12
tests/arch/xilinx/xilinx_dffopt.ys
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@ -5,7 +5,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;
@ -52,7 +52,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;
@ -100,7 +100,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;
@ -137,7 +137,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;
@ -183,7 +183,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;
@ -232,7 +232,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
output wire [7:0] o;
output wire [0:0] o;
wire [7:0] tmp ;