mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00
Code Activity

Fix tests for check in equiv_opt

Browse source
This commit is contained in:
Jannis Harder 2022-08-25 14:24:31 +02:00
parent 0516307637
commit 81906aa627
13 changed files with 31 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/arch/xilinx/opt_lut_ins.ys
View file

@ -18,6 +18,7 @@ end
EOF
read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
design -load postopt