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Fix tests for check in equiv_opt

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Jannis Harder 2022-08-25 14:24:31 +02:00
parent 0516307637
commit 81906aa627
13 changed files with 31 additions and 15 deletions
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tests/arch/ice40/ice40_opt.ys
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@ -21,6 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*