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Fix tests for check in equiv_opt

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This commit is contained in:
Jannis Harder 2022-08-25 14:24:31 +02:00
parent 0516307637
commit 81906aa627
13 changed files with 31 additions and 15 deletions
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3
tests/arch/ice40/bug1597.ys
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@ -3,7 +3,7 @@ module top (
input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
PIN_19,
);
assign USBPU = 0;
@ -67,6 +67,7 @@ module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output w
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
endmodule
EOT
read_verilog -lib +/ice40/cells_sim.v
hierarchy -top top
flatten
equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40

1
tests/arch/ice40/ice40_opt.ys
View file

@ -21,6 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*