mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 13:28:59 +00:00
Code Activity

opt_expr: remove commented log statements. NFC

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-03-20 12:27:33 +01:00
parent 888e01290b
commit 8190036676
1 changed files with 0 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
passes/opt/opt_expr.cc
View file

@ -126,7 +126,6 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
cell->type.c_str(), cell->name.c_str(), info.c_str(), cell->type.c_str(), cell->name.c_str(), info.c_str(),
module->name.c_str(), log_signal(Y), log_signal(out_val)); module->name.c_str(), log_signal(Y), log_signal(out_val));
// log_cell(cell);
assign_map.add(Y, out_val); assign_map.add(Y, out_val);
module->connect(Y, out_val); module->connect(Y, out_val);
module->remove(cell); module->remove(cell);
@ -494,7 +493,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
std::vector<Cell*> module_cells = module->cells(); std::vector<Cell*> module_cells = module->cells();
auto iterator = [&](auto&& replace_cell) { auto iterator = [&](auto&& replace_cell) {
if (sort_fails >= effort) { if (sort_fails >= effort) {
// log("Running on unsorted")
for (auto cell : module_cells) for (auto cell : module_cells)
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type))
replace_cell(cell); replace_cell(cell);