mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 06:13:41 +00:00
Code Activity

test_cell: Fix $bweqx

Browse source
This commit is contained in:
Krystine Sherwin 2025-04-22 10:05:29 +12:00
parent 9399c0cfd5
commit 8186d67ad7
No known key found for this signature in database
1 changed files with 3 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/tests/test_cell.cc
View file

@ -433,13 +433,13 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
int a_size = GetSize(cell->getPort(ID::A)); int a_size = GetSize(cell->getPort(ID::A));
wire = module->addWire(ID::B); wire = module->addWire(ID::B);
wire->width = a_size; wire->width = a_size;
wire->port_output = true; wire->port_input = true;
cell->setPort(ID::B, wire); cell->setPort(ID::B, wire);
if (cell_type == ID($bwmux)) if (cell_type == ID($bwmux))
{ {
wire = module->addWire(ID::S); wire = module->addWire(ID::S);
wire->width = a_size; wire->width = a_size;
wire->port_output = true; wire->port_input = true;
cell->setPort(ID::S, wire); cell->setPort(ID::S, wire);
} }
wire = module->addWire(ID::Y); wire = module->addWire(ID::Y);
@ -1017,10 +1017,8 @@ struct TestCellPass : public Pass {
{ {
cell_types[ID($eqx)] = "ABSY"; cell_types[ID($eqx)] = "ABSY";
cell_types[ID($nex)] = "ABSY"; cell_types[ID($nex)] = "ABSY";
}
// $bweqx is additionally unsupported by ConstEval
if (nosat && techmap_cmd.compare("techmap -assert") != 0 && noeval)
cell_types[ID($bweqx)] = "A"; cell_types[ID($bweqx)] = "A";
}
cell_types[ID($ge)] = "ABSY"; cell_types[ID($ge)] = "ABSY";
cell_types[ID($gt)] = "ABSY"; cell_types[ID($gt)] = "ABSY";