diff --git a/tests/csa_tree/csa_tree_alu_chains.ys b/tests/csa_tree/csa_tree_alu_chains.ys
new file mode 100644
index 000000000..ada1368dc
--- /dev/null
+++ b/tests/csa_tree/csa_tree_alu_chains.ys
@@ -0,0 +1,96 @@
+read_verilog <<EOT
+module alu_add3(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_add4(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_add5(
+	input [11:0] a, b, c, d, e,
+	output [11:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_add8(
+	input [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_add16(
+	input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [15:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
+	+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 14 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+design -reset
diff --git a/tests/csa_tree/csa_tree_alu_macc_edge_cases.ys b/tests/csa_tree/csa_tree_alu_macc_edge_cases.ys
new file mode 100644
index 000000000..6751a58ed
--- /dev/null
+++ b/tests/csa_tree/csa_tree_alu_macc_edge_cases.ys
@@ -0,0 +1,285 @@
+read_verilog <<EOT
+module alu_add2(
+	input [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a + b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+select -assert-none t:$fa
+select -assert-none t:$add
+select -assert-none t:$sub
+select -assert-count 1 t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_sub2(
+	input [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a - b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+select -assert-none t:$fa
+select -assert-none t:$add
+select -assert-none t:$sub
+select -assert-count 1 t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_compare(
+	input [7:0] a, b,
+	output y
+);
+	assign y = (a < b);
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+select -assert-none t:$fa
+select -assert-none t:$add
+select -assert-none t:$sub
+select -assert-count 1 t:$alu
+design -reset
+
+read_verilog <<EOT
+module macc_mul(
+	input [7:0] a, b, c,
+	output [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset
+
+read_verilog <<EOT
+module alu_fanout(
+	input [7:0] a, b, c,
+	output [7:0] mid, y
+);
+	wire [7:0] ab = a + b;
+	assign mid = ab;
+	assign y = ab + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-none t:$fa
+select -assert-count 2 t:$alu
+design -reset
+
+read_verilog <<EOT
+module macc_2port(
+	input [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a + b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$fa
+design -reset
+
+read_verilog <<EOT
+module alu_idempotent(
+	input [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+
+csa_tree
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$sub
+select -assert-none t:$alu
+
+csa_tree
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$sub
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module alu_mixed_width(
+	input [7:0] a,
+	input [3:0] b,
+	input [15:0] c,
+	input [7:0] d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_signed(
+	input signed [7:0] a, b, c, d,
+	output signed [9:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module fir_4tap_alu(
+	input clk,
+	input [15:0] x, c0, c1, c2, c3,
+	output reg [31:0] y
+);
+	reg [15:0] x1, x2, x3;
+	always @(posedge clk) begin
+		x1 <= x;
+		x2 <= x1;
+		x3 <= x2;
+	end
+
+	wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
+	always @(posedge clk) y <= sum;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-min 1 t:$dff
+design -reset
+
+read_verilog <<EOT
+module alu_mixed_sign(
+	input signed [7:0] a,
+	input [7:0] b,
+	input signed [7:0] c,
+	output signed [9:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_wide32(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_single(
+	input [7:0] a,
+	output [7:0] y
+);
+	assign y = a;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+select -assert-none t:$fa
+select -assert-none t:$add
+select -assert-none t:$sub
+select -assert-none t:$alu
+design -reset
+
+read_verilog <<EOT
+module macc_mul_survives(
+	input [7:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a * b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset
diff --git a/tests/csa_tree/csa_tree_alu_macc_equiv.ys b/tests/csa_tree/csa_tree_alu_macc_equiv.ys
new file mode 100644
index 000000000..a8c60ac1a
--- /dev/null
+++ b/tests/csa_tree/csa_tree_alu_macc_equiv.ys
@@ -0,0 +1,179 @@
+read_verilog <<EOT
+module equiv_alu_add3(
+	input [3:0] a, b, c,
+	output [3:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_alu_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_alu_add8(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_alu_signed(
+	input signed [3:0] a, b, c, d,
+	output signed [5:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_alu_sub_mixed(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_alu_sub_all(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+equiv_opt csa_tree
+design -load postopt
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_macc_add3(
+	input [3:0] a, b, c,
+	output [3:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_macc_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_macc_add8(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_macc_signed(
+	input signed [3:0] a, b, c, d,
+	output signed [5:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
diff --git a/tests/csa_tree/csa_tree_alu_macc_sim.ys b/tests/csa_tree/csa_tree_alu_macc_sim.ys
new file mode 100644
index 000000000..7f76ac476
--- /dev/null
+++ b/tests/csa_tree/csa_tree_alu_macc_sim.ys
@@ -0,0 +1,116 @@
+read_verilog <<EOT
+module sim_alu_add4(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+
+sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
+sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
+sat -set a 255 -set b 255 -set c 255 -set d 255 -prove y 252
+design -reset
+
+read_verilog <<EOT
+module sim_alu_sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+
+sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
+design -reset
+
+read_verilog <<EOT
+module sim_alu_sub_all(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+
+sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252
+design -reset
+
+read_verilog <<EOT
+module sim_macc_add4(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+
+sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
+sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
+design -reset
+
+read_verilog <<EOT
+module sim_macc_add8(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+
+sat -set a 1 -set b 2 -set c 3 -set d 4 -set e 5 -set f 6 -set g 7 -set h 8 -prove y 36
+sat -set a 0 -set b 0 -set c 0 -set d 0 -set e 0 -set f 0 -set g 0 -set h 0 -prove y 0
+sat -set a 32 -set b 32 -set c 32 -set d 32 -set e 32 -set f 32 -set g 32 -set h 32 -prove y 0
+design -reset
+
+read_verilog <<EOT
+module sim_macc_sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+
+sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
+design -reset
diff --git a/tests/csa_tree/csa_tree_alu_sub_chains.ys b/tests/csa_tree/csa_tree_alu_sub_chains.ys
new file mode 100644
index 000000000..c7ff5663a
--- /dev/null
+++ b/tests/csa_tree/csa_tree_alu_sub_chains.ys
@@ -0,0 +1,79 @@
+read_verilog <<EOT
+module alu_sub_3op(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a - b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_sub_all(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module alu_sub_signed(
+	input signed [7:0] a, b, c, d,
+	output signed [9:0] y
+);
+	assign y = a + b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt_clean
+csa_tree
+opt_clean
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$alu
+select -assert-none t:$sub
+design -reset
diff --git a/tests/csa_tree/csa_tree_macc.ys b/tests/csa_tree/csa_tree_macc.ys
new file mode 100644
index 000000000..27684e0ed
--- /dev/null
+++ b/tests/csa_tree/csa_tree_macc.ys
@@ -0,0 +1,141 @@
+# Tests for csa_tree operating on $macc cells (post-alumacc)
+# After alumacc, chains of adds get merged into a single $macc cell.
+# The csa_tree pass should decompose it into FA + final add.
+
+# 3-input add merged into $macc
+read_verilog <<EOT
+module macc_add3(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$macc t:$macc_v2 %u
+design -reset
+
+# 4-input add merged into $macc
+read_verilog <<EOT
+module macc_add4(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$macc t:$macc_v2 %u
+design -reset
+
+# 5-input add merged into $macc
+read_verilog <<EOT
+module macc_add5(
+	input [11:0] a, b, c, d, e,
+	output [11:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$macc t:$macc_v2 %u
+design -reset
+
+# 8-input add merged into $macc
+read_verilog <<EOT
+module macc_add8(
+	input [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-none t:$macc t:$macc_v2 %u
+design -reset
+
+read_verilog <<EOT
+module macc_sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module macc_const(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c + 8'd42;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module macc_two(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y1, y2
+);
+	assign y1 = a + b + c + d;
+	assign y2 = e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+csa_tree
+opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-count 4 t:$fa
+select -assert-count 2 t:$add
+design -reset