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Merge pull request #3624 from jix/sim_yw

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Changes to support SBY trace generation with the sim command
This commit is contained in:
Miodrag Milanović 2023-01-23 16:55:17 +01:00 • committed by GitHub
commit 8180cc4325
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15 changed files with 1722 additions and 113 deletions
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10
passes/cmds/setundef.cc
View file

@ -502,7 +502,15 @@ struct SetundefPass : public Pass {
}
}
module->rewrite_sigspecs(worker);
for (auto &it : module->cells_)
if (!it.second->get_bool_attribute(ID::xprop_decoder))
it.second->rewrite_sigspecs(worker);
for (auto &it : module->processes)
it.second->rewrite_sigspecs(worker);
for (auto &it : module->connections_) {
worker(it.first);
worker(it.second);
}
if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)
{

3
passes/cmds/xprop.cc
View file

@ -252,7 +252,8 @@ struct XpropWorker
}
if (!driven_orig.empty()) {
module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
auto decoder = module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
decoder->set_bool_attribute(ID::xprop_decoder);
}
if (!driven_never_x.first.empty()) {
module->connect(driven_never_x);