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Added Xilinx example for Basys3 board

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This commit is contained in:
Clifford Wolf 2015-02-01 17:09:34 +01:00
parent 6978f3a77b
commit 816fe6bbe0
9 changed files with 84 additions and 1 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -68,6 +68,7 @@ struct SynthXilinxPass : public Pass {
log("The following commands are executed by this synthesis command:\n");
log("\n");
log(" begin:\n");
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@ -151,6 +152,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "begin"))
{
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
}