mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-19 12:23:39 +00:00
Code Activity

Added Xilinx example for Basys3 board

Browse source
This commit is contained in:
Clifford Wolf 2015-02-01 17:09:34 +01:00
parent 6978f3a77b
commit 816fe6bbe0
9 changed files with 84 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

21
techlibs/xilinx/example_basys3/example.v Normal file
View file

@ -0,0 +1,21 @@
module example(CLK, LD);
input CLK;
output [15:0] LD;
wire clock;
reg [15:0] leds;
BUFG CLK_BUF (.I(CLK), .O(clock));
OBUF LD_BUF[15:0] (.I(leds), .O(LD));
parameter COUNTBITS = 26;
reg [COUNTBITS-1:0] counter;
always @(posedge CLK) begin
counter <= counter + 1;
if (counter[COUNTBITS-1])
leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
else
leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
end
endmodule