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Added Xilinx example for Basys3 board

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This commit is contained in:
Clifford Wolf 2015-02-01 17:09:34 +01:00
parent 6978f3a77b
commit 816fe6bbe0
9 changed files with 84 additions and 1 deletions
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6
techlibs/xilinx/cells_sim.v
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@ -19,7 +19,7 @@ module OBUF(output O, input I);
assign O = I;
endmodule
module BUFGP(output O, input I);
module BUFG(output O, input I);
assign O = I;
endmodule
@ -27,6 +27,10 @@ module OBUFT(output O, input I, T);
assign O = T ? 1'bz : I;
endmodule
module IOBUF(inout IO, output O, input I, T);
assign O = IO, IO = T ? 1'bz : I;
endmodule
module INV(output O, input I);
assign O = !I;
endmodule