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Merge pull request #800 from whitequark/write_verilog_tribuf

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write_verilog: write $tribuf cell as ternary
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Clifford Wolf 2019-01-27 09:23:41 +01:00 committed by GitHub
parent bf798a9020 3d7925ad9f
commit 81581f24fc
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1 changed files with 12 additions and 0 deletions
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12
backends/verilog/verilog_backend.cc
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@ -816,6 +816,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$tribuf")
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Y"));
f << stringf(" = ");
dump_sigspec(f, cell->getPort("\\EN"));
f << stringf(" ? ");
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
return true;
}
if (cell->type == "$slice") if (cell->type == "$slice")
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());