mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 03:45:52 +00:00
Code Activity

Update to fix infinite loop

Browse source
This commit is contained in:
Akash Levy 2024-08-14 13:40:30 -07:00
parent 83dfdd9dd5
commit 8118380726
1 changed files with 7 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/cmds/splitfanout.cc
View file

@ -108,9 +108,13 @@ struct SplitfanoutWorker
// Connect the new cell to the user // Connect the new cell to the user
if (std::get<1>(bit_user) == IdString()) { // is wire if (std::get<1>(bit_user) == IdString()) { // is wire
Wire *wire = module->wire(std::get<0>(bit_user)); Wire *old_wire = module->wire(std::get<0>(bit_user));
SigSpec spec(wire, std::get<2>(bit_user), GetSize(outsig)); Wire *new_wire = module->addWire(NEW_ID, old_wire);
new_cell->setPort(outport, spec); module->swap_names(old_wire, new_wire);
old_wire->port_input = false;
old_wire->port_output = false;
SigSpec sig(new_wire, std::get<2>(bit_user), GetSize(outsig));
new_cell->setPort(outport, sig);
} }
else { else {
Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig)); Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));