Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup

CHANGELOG

@@ -2,11 +2,17 @@
 List of major changes and improvements between releases
 =======================================================
 
+
 Yosys 0.9 .. Yosys 0.9-dev
 --------------------------
 
  * Various
-    - Added "script -select"
+    - Added "write_xaiger" backend
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
+    - Added "script -scriptwire
 
 
 Yosys 0.8 .. Yosys 0.8-dev
@@ -32,11 +38,6 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "synth_xilinx -nocarry"
     - Added "synth_xilinx -nowidelut"
     - Added "synth_ecp5 -nowidelut"
-    - Added "write_xaiger" backend
-    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
-    - Added "synth_xilinx -abc9" (experimental)
-    - Added "synth_ice40 -abc9" (experimental)
-    - Added "synth -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 

kernel/yosys.cc

@@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass {
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    script <filename> [<from_label>:<to_label>]\n");
-		log("    script -select [selection]\n");
+		log("    script -scriptwire [selection]\n");
 		log("\n");
 		log("This command executes the yosys commands in the specified file (default\n");
 		log("behaviour), or commands embedded in the constant text value connected to the\n");
@@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		bool select_mode = false;
+		bool scriptwire = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-select") {
+			if (args[argidx] == "-scriptwire") {
-				select_mode = true;
+				scriptwire = true;
 				continue;
 			}
 			break;
 		}
-		if (select_mode) {
+		if (scriptwire) {
 			extra_args(args, argidx, design);
 
 			for (auto mod : design->selected_modules())
@@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass {
 					if (!c.second.is_fully_const())
 						log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
 					auto v = c.second.as_const();
-					Pass::call(design, v.decode_string());
+					Pass::call_on_module(design, mod, v.decode_string());
 				}
 		}
 		else if (args.size() < 2)

passes/techmap/Makefile.inc

@@ -10,6 +10,7 @@ OBJS += passes/techmap/abc.o
 OBJS += passes/techmap/abc9.o
 ifneq ($(ABCEXTERNAL),)
 passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
+passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
 endif
 endif
 

techlibs/ecp5/Makefile.inc

@@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk

techlibs/xilinx/Makefile.inc

@@ -30,8 +30,10 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))

tests/various/script.ys

@@ -9,12 +9,12 @@ read_verilog -formal <<EOT
     endmodule
 
     module other;
-        wire [1023:0] _DELETE = "delete c:bar";
+        wire [1023:0] _DELETE = "cd; delete c:bar";
     endmodule
 EOT
 
-script -select w:_RUNME*
+script -scriptwire w:_RUNME*
 
 select w:_DELETE
-script -select
+script -scriptwire
 select -assert-count 1 t:foo