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abc9: for sccs, create a new wire instead of using entirety of existing

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This commit is contained in:
Eddie Hung 2020-03-06 10:30:07 -08:00
parent 91a7a74ac4
commit 80dcc8a0d1
1 changed files with 7 additions and 7 deletions
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14
passes/techmap/abc9_ops.cc
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@ -93,9 +93,10 @@ void check(RTLIL::Design *design)
void mark_scc(RTLIL::Module *module) void mark_scc(RTLIL::Module *module)
{ {
// For every unique SCC found, (arbitrarily) find the first // For every unique SCC found, (arbitrarily) find the first
// cell in the component, and convert all wires driven by // cell in the component, and replace its output connections
// its output ports into a new PO, and drive its previous // with a new wire driven by the old connection but with a
// sinks with a new PI // special (* abc9_scc *) attribute set (which is used by
// write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen; pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID(abc9_scc_id)); auto it = cell->attributes.find(ID(abc9_scc_id));
@ -109,11 +110,10 @@ void mark_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) { for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue; if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) { if (cell->output(c.first)) {
SigBit b = c.second.as_bit(); Wire *w = module->addWire(NEW_ID, GetSize(c.second));
// TODO: Don't be as heavy handed as to
// mark the entire wire as part of the scc
Wire *w = b.wire;
w->set_bool_attribute(ID(abc9_scc)); w->set_bool_attribute(ID(abc9_scc));
module->connect(w, c.second);
c.second = w;
} }
} }
} }