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Docs: Tidying
Fix error on duplicated heading. Drop `cmd_ref`_ link (everything already uses :doc:`cmd_ref`).
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2 changed files with 2 additions and 4 deletions
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@ -311,8 +311,8 @@ cells, as the net-names are usually suppressed in the circuit diagram if they
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are auto-generated. Note that the output is in the RTLIL representation,
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described in :doc:`/yosys_internals/formats/rtlil_rep`.
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Interactive Design Investigation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Design Investigation
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~~~~~~~~~~~~~~~~~~~~
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Yosys can also be used to investigate designs (or netlists created from other
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tools).
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