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genrtlil: don't avoid emitting flops for nosync

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This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:37:08 +02:00
parent 1801abf30a
commit 80bdbaa010
2 changed files with 5 additions and 12 deletions
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12
frontends/ast/genrtlil.cc
View file

@ -406,18 +406,6 @@ struct AST_INTERNAL::ProcessGenerator
if (GetSize(syncrule->signal) != 1) if (GetSize(syncrule->signal) != 1)
always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n"); always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n");
addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
// Automatic (nosync) variables must not become flip-flops: remove
// them from clocked sync rules so that proc_dff does not infer
// an unnecessary register for a purely combinational temporary.
syncrule->actions.erase(
std::remove_if(syncrule->actions.begin(), syncrule->actions.end(),
[](const RTLIL::SigSig &ss) {
for (auto &chunk : ss.first.chunks())
if (chunk.wire && chunk.wire->get_bool_attribute(ID::nosync))
return true;
return false;
}),
syncrule->actions.end());
proc->syncs.push_back(syncrule); proc->syncs.push_back(syncrule);
} }
if (proc->syncs.empty()) { if (proc->syncs.empty()) {

5
tests/verilog/automatic_lifetime.ys
View file

@ -15,6 +15,7 @@ module t1(input a, b, c, output reg y);
endmodule endmodule
EOF EOF
proc proc
opt_clean
async2sync async2sync
# no state elements for tmp # no state elements for tmp
select -assert-none t:$dff t:$dlatch %% select -assert-none t:$dff t:$dlatch %%
@ -39,6 +40,7 @@ module t2(input [3:0] a, b, input sel, output reg [3:0] y, output reg co);
endmodule endmodule
EOF EOF
proc proc
opt_clean
async2sync async2sync
select -assert-none t:$dff t:$dlatch %% select -assert-none t:$dff t:$dlatch %%
sat -verify -prove-asserts -show-all sat -verify -prove-asserts -show-all
@ -59,6 +61,7 @@ module t3(input clk, rst, input [7:0] data, output reg [7:0] result);
endmodule endmodule
EOF EOF
proc proc
opt_clean
# Exactly one DFF (for result), zero latches, no DFF for tmp # Exactly one DFF (for result), zero latches, no DFF for tmp
select -assert-count 1 t:$dff %% select -assert-count 1 t:$dff %%
select -assert-none t:$dlatch %% select -assert-none t:$dlatch %%
@ -80,6 +83,7 @@ module t4(input [7:0] a, b, input sub, output reg [7:0] y);
endmodule endmodule
EOF EOF
proc proc
opt_clean
async2sync async2sync
select -assert-none t:$dff t:$dlatch %% select -assert-none t:$dff t:$dlatch %%
sat -verify -prove-asserts -show-all sat -verify -prove-asserts -show-all
@ -100,5 +104,6 @@ module t5(input en, d, output reg q);
endmodule endmodule
EOF EOF
proc proc
opt_clean
# No latch for tmp — X propagates instead of old value # No latch for tmp — X propagates instead of old value
select -assert-none t:$dff t:$dlatch %% select -assert-none t:$dff t:$dlatch %%