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genrtlil: don't avoid emitting flops for nosync

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This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:37:08 +02:00
parent 1801abf30a
commit 80bdbaa010
2 changed files with 5 additions and 12 deletions
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5
tests/verilog/automatic_lifetime.ys
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@ -15,6 +15,7 @@ module t1(input a, b, c, output reg y);
endmodule
EOF
proc
opt_clean
async2sync
# no state elements for tmp
select -assert-none t:$dff t:$dlatch %%
@ -39,6 +40,7 @@ module t2(input [3:0] a, b, input sel, output reg [3:0] y, output reg co);
endmodule
EOF
proc
opt_clean
async2sync
select -assert-none t:$dff t:$dlatch %%
sat -verify -prove-asserts -show-all
@ -59,6 +61,7 @@ module t3(input clk, rst, input [7:0] data, output reg [7:0] result);
endmodule
EOF
proc
opt_clean
# Exactly one DFF (for result), zero latches, no DFF for tmp
select -assert-count 1 t:$dff %%
select -assert-none t:$dlatch %%
@ -80,6 +83,7 @@ module t4(input [7:0] a, b, input sub, output reg [7:0] y);
endmodule
EOF
proc
opt_clean
async2sync
select -assert-none t:$dff t:$dlatch %%
sat -verify -prove-asserts -show-all
@ -100,5 +104,6 @@ module t5(input en, d, output reg q);
endmodule
EOF
proc
opt_clean
# No latch for tmp — X propagates instead of old value
select -assert-none t:$dff t:$dlatch %%