3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-31 06:07:47 +00:00

genrtlil: don't avoid emitting flops for nosync

This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:37:08 +02:00
parent 1801abf30a
commit 80bdbaa010
2 changed files with 5 additions and 12 deletions

View file

@ -406,18 +406,6 @@ struct AST_INTERNAL::ProcessGenerator
if (GetSize(syncrule->signal) != 1)
always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n");
addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
// Automatic (nosync) variables must not become flip-flops: remove
// them from clocked sync rules so that proc_dff does not infer
// an unnecessary register for a purely combinational temporary.
syncrule->actions.erase(
std::remove_if(syncrule->actions.begin(), syncrule->actions.end(),
[](const RTLIL::SigSig &ss) {
for (auto &chunk : ss.first.chunks())
if (chunk.wire && chunk.wire->get_bool_attribute(ID::nosync))
return true;
return false;
}),
syncrule->actions.end());
proc->syncs.push_back(syncrule);
}
if (proc->syncs.empty()) {