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More abc_new tests.

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nella 2026-05-05 10:51:04 +02:00
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tests/techmap/abc_new_no_script.ys Normal file
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read_verilog <<EOT
module top(input [3:0] a, input [3:0] b, output [3:0] y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +8/ +4" 3
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect error "Missing mapping \(no 'M' section\)" 1
abc_new -liberty ../../examples/cmos/cmos_cells.lib