From bbd132f6ba026efcb647a9634850dbbedb636d34 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 10:10:06 -0700
Subject: [PATCH 01/10] updated extract_reduce to not consider xnors

---
 passes/techmap/extract_reduce.cc | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 376f2a9d3..6b538c589 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -30,7 +30,6 @@ struct ExtractReducePass : public Pass
 		And,
 		Or,
 		Xor,
-		Xnor,
 		Mux
 	};
 
@@ -51,8 +50,8 @@ struct ExtractReducePass : public Pass
 		log("to map the design to only $_AND_ cells, run extract_reduce, map the remaining\n");
 		log("parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.\n");
 		log("\n");
-		log("Silimate has modified this pass to support word-level cells ($and, $or, $xor,\n");
-		log("and $xnor) as well as the single-bit cells ($_AND_, $_OR_, $_XOR_, and $_XNOR_).\n");
+		log("Silimate has modified this pass to support word-level cells ($and, $or, \n");
+		log("and $xor) as well as the single-bit cells ($_AND_, $_OR_, and $_XOR_).\n");
 		log("Mux cells ($mux, $_MUX_) can also be reduced to $pmux cells with the mods.\n");
 		log("\n");
 		log("    -allow-off-chain\n");
@@ -85,12 +84,10 @@ struct ExtractReducePass : public Pass
 		return (cell->type == ID($_AND_) && gt == GateType::And) ||
 				(cell->type == ID($_OR_) && gt == GateType::Or) ||
 				(cell->type == ID($_XOR_) && gt == GateType::Xor) ||
-				(cell->type == ID($_XNOR_) && gt == GateType::Xnor) ||
 				(cell->type == ID($_MUX_) && gt == GateType::Mux) ||
 				(cell->type == ID($and) && IsSingleBit(cell) && gt == GateType::And) ||
 				(cell->type == ID($or) && IsSingleBit(cell) && gt == GateType::Or) ||
 				(cell->type == ID($xor) && IsSingleBit(cell) && gt == GateType::Xor) ||
-				(cell->type == ID($xnor) && IsSingleBit(cell) && gt == GateType::Xnor) ||
 				(cell->type == ID($mux) && IsSingleBit(cell) && gt == GateType::Mux);
 	}
 
@@ -176,8 +173,6 @@ struct ExtractReducePass : public Pass
 					gt = GateType::Or;
 				else if (cell->type == ID($_XOR_))
 					gt = GateType::Xor;
-				else if (cell->type == ID($_XNOR_))
-					gt = GateType::Xnor;
 				else if (cell->type == ID($_MUX_))
 					gt = GateType::Mux;
 				else if (cell->type == ID($and) && IsSingleBit(cell))
@@ -186,8 +181,6 @@ struct ExtractReducePass : public Pass
 					gt = GateType::Or;
 				else if (cell->type == ID($xor) && IsSingleBit(cell))
 					gt = GateType::Xor;
-				else if (cell->type == ID($xnor) && IsSingleBit(cell))
-					gt = GateType::Xnor;
 				else if (cell->type == ID($mux) && IsSingleBit(cell))
 					gt = GateType::Mux;
 				else
@@ -352,7 +345,7 @@ struct ExtractReducePass : public Pass
 						SigSpec input, sel;
 						for (auto it : sources) {
 							bool cond;
-							if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor) || head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor))
+							if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor))
 								cond = it.second & 1;
 							else
 								cond = it.second != 0;
@@ -372,8 +365,6 @@ struct ExtractReducePass : public Pass
 							module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
 						} else if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor)) {
 							module->addReduceXor(NEW_ID2_SUFFIX("reduce_xor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
-						} else if (head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor)) {
-							module->addReduceXnor(NEW_ID2_SUFFIX("reduce_xnor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
 						} else if (head_cell->type == ID($_MUX_) || head_cell->type == ID($mux)) {
 							module->addPmux(NEW_ID2_SUFFIX("pmux"), State::Sx, input, sel, output, cell->get_src_attribute()); // SILIMATE: Improve the naming
 						} else {

From 8f5f4ecab4a1303c61f6482d4e728fc9da1a9d34 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 10:11:17 -0700
Subject: [PATCH 02/10] inital extract_reduce tests

---
 tests/silimate/extract_reduce.ys | 605 +++++++++++++++++++++++++++++++
 1 file changed, 605 insertions(+)
 create mode 100644 tests/silimate/extract_reduce.ys

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
new file mode 100644
index 000000000..1fbf1a06c
--- /dev/null
+++ b/tests/silimate/extract_reduce.ys
@@ -0,0 +1,605 @@
+###################################################################
+# Extract Reduce AND Gates Tests
+###################################################################
+
+log -header "Simple AND chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] & a[1] & a[2] & a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+
+design -reset
+log -pop
+
+
+
+log -header "AND chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w1, w2, w3, w4;
+
+  assign w1 = a[0] & a[1];
+  assign w2 = a[2] & a[3];
+  assign w3 = a[4] & a[5];
+  assign w4 = w1 & w2;
+  assign x = w3 & w4;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] & a[1];
+  assign w2 = w1 & a[2];
+  assign w3 = w2 & a[3];
+  assign x = w3 & a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] & a[1];
+  assign w2 = w1 & a[2];
+  assign w3 = w2 & a[3];
+  assign x = w3 & a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+###################################################################
+# Extract Reduce OR Gates Tests
+###################################################################
+
+log -header "Simple OR chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] | a[1] | a[2] | a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "OR chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w1, w2, w3, w4;
+
+  assign w1 = a[0] | a[1];
+  assign w2 = a[2] | a[3];
+  assign w3 = a[4] | a[5];
+  assign w4 = w1 | w2;
+  assign x = w3 | w4;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] | a[1];
+  assign w2 = w1 | a[2];
+  assign w3 = w2 | a[3];
+  assign x = w3 | a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 2 t:$reduce_or
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] | a[1];
+  assign w2 = w1 | a[2];
+  assign w3 = w2 | a[3];
+  assign x = w3 | a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 2 t:$reduce_or
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+###################################################################
+# Extract Reduce XOR Gates Tests
+###################################################################
+
+log -header "Simple XOR chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor
+
+design -reset
+log -pop
+
+
+
+log -header "XOR chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w1, w2, w3, w4;
+
+  assign w1 = a[0] ^ a[1];
+  assign w2 = a[2] ^ a[3];
+  assign w3 = a[4] ^ a[5];
+  assign w4 = w1 ^ w2;
+  assign x = w3 ^ w4;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] ^ a[1];
+  assign w2 = w1 ^ a[2];
+  assign w3 = w2 ^ a[3];
+  assign x = w3 ^ a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = a[0] ^ a[1];
+  assign w2 = w1 ^ a[2];
+  assign w3 = w2 ^ a[3];
+  assign x = w3 ^ a[4];
+
+  // Off-chain use of w2
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+
+
+###################################################################
+# Extract PMUX from MUX Chains Tests
+###################################################################
+
+log -header "Simple MUX chain to PMUX"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [3:0] a,
+  output wire x
+);
+  wire w1, w2;
+
+  assign w1 = sel[0] ? a[1] : a[0];
+  assign w2 = sel[1] ? a[2] : w1;
+  assign x  = sel[2] ? a[3] : w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+
+design -reset
+log -pop
+
+
+# TODO
+log -header "MUX chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [3:0] a,
+  output wire x
+);
+  wire w1, w2;
+
+  assign w1 = sel[0] ? a[1] : a[0];
+  assign w2 = sel[1] ? a[2] : a[3];
+  assign x  = sel[2] ? w1 : w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain MUX chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] sel,
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = sel[0] ? a[1] : a[0];
+  assign w2 = sel[1] ? a[2] : w1;
+  assign w3 = sel[2] ? a[3] : w2;
+  assign x  = sel[3] ? a[4] : w3;
+
+  // Off-chain use of intermediate wire
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got two pmuxes
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+
+# Check that both pmuxes have input width of 3
+select -assert-none t:$pmux r:S_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+
+log -header "Allow off-chain MUX chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] sel,
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w1, w2, w3;
+
+  assign w1 = sel[0] ? a[1] : a[0];
+  assign w2 = sel[1] ? a[2] : w1;
+  assign w3 = sel[2] ? a[3] : w2;
+  assign x  = sel[3] ? a[4] : w3;
+
+  assign y = w2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got two $pmux
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+
+# Check that one pmux has an input width of 3 
+# and the other has an input width of 5
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=5 %i
+
+design -reset
+log -pop

From 101f775b64c5bb3e555749e3f25ecd74e04e6765 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 10:18:20 -0700
Subject: [PATCH 03/10] added extra test for muxes

---
 tests/silimate/extract_reduce.ys | 47 +++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
index 1fbf1a06c..6cf9880fd 100644
--- a/tests/silimate/extract_reduce.ys
+++ b/tests/silimate/extract_reduce.ys
@@ -485,7 +485,7 @@ design -reset
 log -pop
 
 
-# TODO
+
 log -header "MUX chain with multiple branches"
 log -push
 design -reset
@@ -520,6 +520,51 @@ log -pop
 
 
 
+log -header "MUX chain with multiple uneven branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] sel,
+  input wire [6:0] a,
+  output wire x
+);
+  wire w1, w2, w3, w4, w5;
+
+  assign w1 = sel[0] ? a[1] : a[0];
+  assign w2 = sel[1] ? a[2] : w1;
+  assign w3 = sel[2] ? a[3] : w2;
+  assign w4 = sel[3] ? w3 : w5;
+  assign w5 = sel[5] ? a[4] : a[5];
+  assign x  = sel[4] ? w4 : a[6];
+endmodule
+EOF
+check -assert
+
+autoname
+write_json dump_pre.json
+exec -- netlistsvg dump_pre.json -o dump_pre.svg
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+autoname
+write_json dump_post.json
+exec -- netlistsvg dump_post.json -o dump_post.svg
+
+# Check we got a single pmux
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+
+design -reset
+log -pop
+
+
+
 log -header "No off-chain MUX chain"
 log -push
 design -reset

From 8991707dee9db0f3892ebe11f614e30564a09c48 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 10:19:54 -0700
Subject: [PATCH 04/10] zero indexed wires

---
 tests/silimate/extract_reduce.ys | 174 +++++++++++++++----------------
 1 file changed, 87 insertions(+), 87 deletions(-)

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
index 6cf9880fd..888f0182a 100644
--- a/tests/silimate/extract_reduce.ys
+++ b/tests/silimate/extract_reduce.ys
@@ -39,13 +39,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = a[2] & a[3];
-  assign w3 = a[4] & a[5];
-  assign w4 = w1 & w2;
-  assign x = w3 & w4;
+  assign w0 = a[0] & a[1];
+  assign w1 = a[2] & a[3];
+  assign w2 = a[4] & a[5];
+  assign w3 = w0 & w1;
+  assign x = w2 & w3;
 endmodule
 EOF
 check -assert
@@ -75,15 +75,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = w1 & a[2];
-  assign w3 = w2 & a[3];
-  assign x = w3 & a[4];
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -116,15 +116,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = w1 & a[2];
-  assign w3 = w2 & a[3];
-  assign x = w3 & a[4];
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -188,13 +188,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = a[2] | a[3];
-  assign w3 = a[4] | a[5];
-  assign w4 = w1 | w2;
-  assign x = w3 | w4;
+  assign w0 = a[0] | a[1];
+  assign w1 = a[2] | a[3];
+  assign w2 = a[4] | a[5];
+  assign w3 = w0 | w1;
+  assign x = w2 | w3;
 endmodule
 EOF
 check -assert
@@ -224,15 +224,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = w1 | a[2];
-  assign w3 = w2 | a[3];
-  assign x = w3 | a[4];
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -265,15 +265,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = w1 | a[2];
-  assign w3 = w2 | a[3];
-  assign x = w3 | a[4];
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -337,13 +337,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = a[2] ^ a[3];
-  assign w3 = a[4] ^ a[5];
-  assign w4 = w1 ^ w2;
-  assign x = w3 ^ w4;
+  assign w0 = a[0] ^ a[1];
+  assign w1 = a[2] ^ a[3];
+  assign w2 = a[4] ^ a[5];
+  assign w3 = w0 ^ w1;
+  assign x = w2 ^ w3;
 endmodule
 EOF
 check -assert
@@ -373,15 +373,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = w1 ^ a[2];
-  assign w3 = w2 ^ a[3];
-  assign x = w3 ^ a[4];
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -415,15 +415,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = w1 ^ a[2];
-  assign w3 = w2 ^ a[3];
-  assign x = w3 ^ a[4];
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -461,11 +461,11 @@ module top (
   input wire [3:0] a,
   output wire x
 );
-  wire w1, w2;
+  wire w0, w1;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign x  = sel[2] ? a[3] : w2;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign x  = sel[2] ? a[3] : w1;
 endmodule
 EOF
 check -assert
@@ -495,11 +495,11 @@ module top (
   input wire [3:0] a,
   output wire x
 );
-  wire w1, w2;
+  wire w0, w1;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : a[3];
-  assign x  = sel[2] ? w1 : w2;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : a[3];
+  assign x  = sel[2] ? w0 : w1;
 endmodule
 EOF
 check -assert
@@ -529,14 +529,14 @@ module top (
   input wire [6:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4, w5;
+  wire w0, w1, w2, w3, w4;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign w4 = sel[3] ? w3 : w5;
-  assign w5 = sel[5] ? a[4] : a[5];
-  assign x  = sel[4] ? w4 : a[6];
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign w3 = sel[3] ? w2 : w4;
+  assign w4 = sel[5] ? a[4] : a[5];
+  assign x  = sel[4] ? w3 : a[6];
 endmodule
 EOF
 check -assert
@@ -575,15 +575,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign x  = sel[3] ? a[4] : w3;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
 
   // Off-chain use of intermediate wire
-  assign y = w2;
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -618,14 +618,14 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign x  = sel[3] ? a[4] : w3;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
 
-  assign y = w2;
+  assign y = w1;
 endmodule
 EOF
 check -assert

From 2f9e6e08f0ce0f7b20d84cd033264feb6c89c381 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 10:39:33 -0700
Subject: [PATCH 05/10] added tests with constants

---
 tests/silimate/extract_reduce.ys | 165 ++++++++++++++++++++++++++-----
 1 file changed, 139 insertions(+), 26 deletions(-)

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
index 888f0182a..50bb09078 100644
--- a/tests/silimate/extract_reduce.ys
+++ b/tests/silimate/extract_reduce.ys
@@ -22,9 +22,38 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$and
-select -assert-count 1 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "AND chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] a,
+  output wire x
+);
+  assign x = a[0] & a[1] & a[2] & 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
 
 design -reset
 log -pop
@@ -57,9 +86,9 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$and
-select -assert-count 1 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
 
 design -reset
 log -pop
@@ -171,9 +200,38 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$or
-select -assert-count 1 t:$reduce_or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "OR chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] | a[1] | a[2] | 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
 
 design -reset
 log -pop
@@ -206,9 +264,9 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$or
-select -assert-count 1 t:$reduce_or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
 
 design -reset
 log -pop
@@ -320,9 +378,38 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$xor
-select -assert-count 1 t:$reduce_xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "XOR chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] ^ a[1] ^ a[2] ^ 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
 
 design -reset
 log -pop
@@ -355,9 +442,9 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check final design has correct number of gates
+# Check final design has correct number of gates and inputs
 select -assert-count 0 t:$xor
-select -assert-count 1 t:$reduce_xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
 
 design -reset
 log -pop
@@ -477,9 +564,43 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check we got a single pmux
+# Check we got a single pmux with the correct input number
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "MUX chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [2:0] a,
+  output wire x
+);
+  wire w0, w1;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign x  = sel[2] ? 1'b1 : w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux with the correct input number
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
 
 design -reset
 log -pop
@@ -511,9 +632,9 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-# Check we got a single pmux
+# Check we got a single pmux with the correct input number
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
 
 design -reset
 log -pop
@@ -541,10 +662,6 @@ endmodule
 EOF
 check -assert
 
-autoname
-write_json dump_pre.json
-exec -- netlistsvg dump_pre.json -o dump_pre.svg
-
 # Check equivalence after extract_reduce
 equiv_opt -assert extract_reduce
 
@@ -552,13 +669,9 @@ equiv_opt -assert extract_reduce
 design -load postopt
 opt_clean
 
-autoname
-write_json dump_post.json
-exec -- netlistsvg dump_post.json -o dump_post.svg
-
-# Check we got a single pmux
+# Check we got a single pmux with the correct input number
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=7 %i
 
 design -reset
 log -pop

From bc2d9d1f337e149fb3ba997fe6cc8436891bfaaf Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 11:10:50 -0700
Subject: [PATCH 06/10] added deeper cases for gates

---
 tests/silimate/extract_reduce.ys | 237 ++++++++++++++++++++++++++++++-
 1 file changed, 236 insertions(+), 1 deletion(-)

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
index 50bb09078..8b642e70c 100644
--- a/tests/silimate/extract_reduce.ys
+++ b/tests/silimate/extract_reduce.ys
@@ -95,7 +95,7 @@ log -pop
 
 
 
-log -header "No off-chain"
+log -header "No off-chain for AND"
 log -push
 design -reset
 read_verilog <<EOF
@@ -176,6 +176,85 @@ select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
 design -reset
 log -pop
 
+
+
+log -header "No off-chain with branches for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
+  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
+  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
 ###################################################################
 # Extract Reduce OR Gates Tests
 ###################################################################
@@ -354,6 +433,85 @@ select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
 design -reset
 log -pop
 
+
+
+log -header "No off-chain with branches for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
+  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_or
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
+  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_or
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
 ###################################################################
 # Extract Reduce XOR Gates Tests
 ###################################################################
@@ -535,6 +693,83 @@ log -pop
 
 
 
+log -header "No off-chain with branches for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
+  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
+  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
 ###################################################################
 # Extract PMUX from MUX Chains Tests
 ###################################################################

From 776479d7aa6448cc06c9105b11acdeb24b6e85fe Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 17:17:39 -0700
Subject: [PATCH 07/10] wip tests

---
 tests/silimate/extract_reduce_gates.ys | 862 +++++++++++++++++++++++++
 tests/silimate/extract_reduce_muxes.ys | 440 +++++++++++++
 2 files changed, 1302 insertions(+)
 create mode 100644 tests/silimate/extract_reduce_gates.ys
 create mode 100644 tests/silimate/extract_reduce_muxes.ys

diff --git a/tests/silimate/extract_reduce_gates.ys b/tests/silimate/extract_reduce_gates.ys
new file mode 100644
index 000000000..c3a505651
--- /dev/null
+++ b/tests/silimate/extract_reduce_gates.ys
@@ -0,0 +1,862 @@
+###################################################################
+# Extract Reduce AND Gates Tests
+###################################################################
+
+log -header "Simple AND chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] & a[1] & a[2] & a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "AND chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] a,
+  output wire x
+);
+  assign x = a[0] & a[1] & a[2] & 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "AND chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3;
+
+  assign w0 = a[0] & a[1];
+  assign w1 = a[2] & a[3];
+  assign w2 = a[4] & a[5];
+  assign w3 = w0 & w1;
+  assign x = w2 & w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+select -assert-count 2 t:$reduce_and
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain with branches for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
+  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for AND"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
+  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+###################################################################
+# Extract Reduce OR Gates Tests
+###################################################################
+
+log -header "Simple OR chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] | a[1] | a[2] | a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "OR chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] | a[1] | a[2] | 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "OR chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3;
+
+  assign w0 = a[0] | a[1];
+  assign w1 = a[2] | a[3];
+  assign w2 = a[4] | a[5];
+  assign w3 = w0 | w1;
+  assign x = w2 | w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$or
+select -assert-count 1 t:$reduce_or
+select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 2 t:$reduce_or
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 2 t:$reduce_or
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain with branches for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
+  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_or
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for OR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
+  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$or
+select -assert-count 2 t:$reduce_or
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+###################################################################
+# Extract Reduce XOR Gates Tests
+###################################################################
+
+log -header "Simple XOR chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "XOR chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] ^ a[1] ^ a[2] ^ 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "XOR chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3;
+
+  assign w0 = a[0] ^ a[1];
+  assign w1 = a[2] ^ a[3];
+  assign w2 = a[4] ^ a[5];
+  assign w3 = w0 ^ w1;
+  assign x = w2 ^ w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$xor
+select -assert-count 1 t:$reduce_xor
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that both gates are 3 bits wide
+select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
+
+  // Off-chain use of w1
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that only one gate has a width of 5 and one gate has a width of 3
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain with branches for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
+  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that both gates are 6 bits wide
+select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Allow off-chain with branches for XOR"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [10:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0;
+
+  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
+  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
+
+  // Off-chain use of w0
+  assign y = w0;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates
+select -assert-count 0 t:$xor
+select -assert-count 2 t:$reduce_xor
+
+# Check that only one gate has a width of 11 and one gate has a width of 6
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
+select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+###################################################################
+# Edge Cases
+###################################################################
+
+log -header "Reconvergence"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] a,
+  output wire y
+);
+  wire w0, w1, w2, w3, w4, w5, w6;
+
+  assign w0 = a[0] & a[1];
+  assign w1 = a[2] & a[3];
+  assign w2 = w0 & w1;
+  assign w3 = w2 & a[4];
+  assign w4 = w2 & a[5];
+  assign w5 = w3 & a[6];
+  assign w6 = w4 & a[7];
+  assign y = w5 & w6;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+# TODO
+log -header "Combinational feedback loop"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire a,
+  output wire y
+);
+  wire w0, w1;
+
+  // Two AND gates feeding each other
+  assign w0 = a & w1;
+  assign w1 = a & w0;
+
+  assign y = w1;
+endmodule
+EOF
+# check -assert
+
+# Check equivalence after extract_reduce
+# equiv_opt -assert extract_reduce
+extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 2 t:$reduce_and
+select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
+select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+
+design -reset
+log -pop
\ No newline at end of file
diff --git a/tests/silimate/extract_reduce_muxes.ys b/tests/silimate/extract_reduce_muxes.ys
new file mode 100644
index 000000000..b5cd3b2a1
--- /dev/null
+++ b/tests/silimate/extract_reduce_muxes.ys
@@ -0,0 +1,440 @@
+log -header "Simple MUX chain to PMUX"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [3:0] a,
+  output wire x
+);
+  wire w0, w1;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign x  = sel[2] ? a[3] : w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux with the correct input number
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "MUX chain with constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [2:0] a,
+  output wire x
+);
+  wire w0, w1;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign x  = sel[2] ? 1'b1 : w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux with the correct input number
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "MUX chain with multiple branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [3:0] a,
+  output wire x
+);
+  wire w0, w1;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : a[3];
+  assign x  = sel[2] ? w0 : w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux with the correct input number
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
+
+design -reset
+log -pop
+
+
+
+log -header "MUX chain with multiple uneven branches"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] sel,
+  input wire [6:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3, w4;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign w3 = sel[3] ? w2 : w4;
+  assign w4 = sel[5] ? a[4] : a[5];
+  assign x  = sel[4] ? w3 : a[6];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got a single pmux with the correct input number
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=7 %i
+
+design -reset
+log -pop
+
+
+
+log -header "No off-chain MUX chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] sel,
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
+
+  // Off-chain use of intermediate wire
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got two pmuxes
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+
+# Check that both pmuxes have input width of 3
+select -assert-none t:$pmux r:S_WIDTH!=3 %i
+
+design -reset
+log -pop
+
+
+
+
+log -header "Allow off-chain MUX chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] sel,
+  input wire [4:0] a,
+  output wire x,
+  output wire y
+);
+  wire w0, w1, w2;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
+
+  assign y = w1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+opt_clean
+
+# Check we got two pmux
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+
+# Check that one pmux has an input width of 3 
+# and the other has an input width of 5
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=5 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Reconverging tree; no off-chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [7:0] sel,
+  input wire [7:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3, w4, w5, w6;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? w4 : w1;
+  assign w3 = sel[3] ? w2 : w5;
+  assign w4 = sel[6] ? a[3] : w6;
+  assign w5 = sel[5] ? a[5] : w4;
+  assign w6 = sel[7] ? a[7] : a[4];
+  assign x  = sel[4] ? a[6] : w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Reconverging tree; yes off-chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [7:0] sel,
+  input wire [7:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3, w4, w5, w6;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? w4 : w1;
+  assign w3 = sel[3] ? w2 : w5;
+  assign w4 = sel[6] ? a[3] : w6;
+  assign w5 = sel[5] ? a[5] : w4;
+  assign w6 = sel[7] ? a[7] : a[4];
+  assign x  = sel[4] ? a[6] : w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=8 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Reusing select inputs"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] sel,
+  input wire [7:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3, w4, w5, w6;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? w4 : w1;
+  assign w3 = sel[3] ? w2 : w5;
+  assign w4 = sel[2] ? a[3] : w6;
+  assign w5 = sel[5] ? a[5] : w4;
+  assign w6 = sel[4] & sel[1] ? a[7] : a[4];
+  assign x  = sel[4] ? a[6] : w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+log -header "Using outputs as select inputs"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [5:0] sel,
+  input wire [7:0] a,
+  output wire x
+);
+  wire w0, w1, w2, w3, w4, w5, w6;
+
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? w4 : w1;
+  assign w3 = sel[3] ? w2 : w5;
+  assign w4 = sel[2] ? a[3] : w6;
+  assign w5 = sel[5] ? a[5] : w4;
+  assign w6 = w[2] ? a[7] : a[4];
+  assign x  = sel[4] ? a[6] : w3;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+
+design -reset
+log -pop
+
+
+
+# TODO check about infinite loop
+log -header "Mux with feedback that causes infinite loop"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] sel,
+  input wire [3:0] a,
+  output wire x
+);
+  wire w0, w1;
+
+  assign w0 = sel[0] ? a[0] : w0;
+  assign w1 = sel[1] ? a[1] : w0;
+  assign x  = sel[2] ? a[2] : w1;
+endmodule
+EOF
+# check -assert
+
+autoname
+write_json dump_pre.json
+exec -- netlistsvg dump_pre.json -o dump_pre.svg
+
+# Check equivalence after extract_reduce
+# equiv_opt -assert extract_reduce
+extract_reduce -allow-off-chain
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+# design -load postopt
+opt_clean
+opt_reduce
+
+autoname
+write_json dump_post.json
+exec -- netlistsvg dump_post.json -o dump_post.svg
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
+select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+
+design -reset
+log -pop
\ No newline at end of file

From 58d903eee6504fe13f4b0d1f32c42dc61483b8d5 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Tue, 1 Apr 2025 17:19:04 -0700
Subject: [PATCH 08/10] deleted old file

---
 tests/silimate/extract_reduce.ys | 998 -------------------------------
 1 file changed, 998 deletions(-)
 delete mode 100644 tests/silimate/extract_reduce.ys

diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
deleted file mode 100644
index 8b642e70c..000000000
--- a/tests/silimate/extract_reduce.ys
+++ /dev/null
@@ -1,998 +0,0 @@
-###################################################################
-# Extract Reduce AND Gates Tests
-###################################################################
-
-log -header "Simple AND chain"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] a,
-  output wire x
-);
-  assign x = a[0] & a[1] & a[2] & a[3];
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$and
-select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "AND chain with constants"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [2:0] a,
-  output wire x
-);
-  assign x = a[0] & a[1] & a[2] & 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$and
-select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "AND chain with multiple branches"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [5:0] a,
-  output wire x
-);
-  wire w0, w1, w2, w3;
-
-  assign w0 = a[0] & a[1];
-  assign w1 = a[2] & a[3];
-  assign w2 = a[4] & a[5];
-  assign w3 = w0 & w1;
-  assign x = w2 & w3;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$and
-select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain for AND"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] & a[1];
-  assign w1 = w0 & a[2];
-  assign w2 = w1 & a[3];
-  assign x = w2 & a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-
-# Check that both gates are 3 bits wide
-select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain for AND"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] & a[1];
-  assign w1 = w0 & a[2];
-  assign w2 = w1 & a[3];
-  assign x = w2 & a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-
-# Check that only one gate has a width of 5 and one gate has a width of 3
-select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
-select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain with branches for AND"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
-  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-
-# Check that both gates are 6 bits wide
-select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain with branches for AND"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
-  assign x  = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-
-# Check that only one gate has a width of 11 and one gate has a width of 6
-select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
-select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-###################################################################
-# Extract Reduce OR Gates Tests
-###################################################################
-
-log -header "Simple OR chain"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] a,
-  output wire x
-);
-  assign x = a[0] | a[1] | a[2] | a[3];
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$or
-select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "OR chain with constants"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] a,
-  output wire x
-);
-  assign x = a[0] | a[1] | a[2] | 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$or
-select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "OR chain with multiple branches"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [5:0] a,
-  output wire x
-);
-  wire w0, w1, w2, w3;
-
-  assign w0 = a[0] | a[1];
-  assign w1 = a[2] | a[3];
-  assign w2 = a[4] | a[5];
-  assign w3 = w0 | w1;
-  assign x = w2 | w3;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$or
-select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain OR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] | a[1];
-  assign w1 = w0 | a[2];
-  assign w2 = w1 | a[3];
-  assign x = w2 | a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$or
-select -assert-count 2 t:$reduce_or
-
-# Check that both gates are 3 bits wide
-select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain for OR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] | a[1];
-  assign w1 = w0 | a[2];
-  assign w2 = w1 | a[3];
-  assign x = w2 | a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$or
-select -assert-count 2 t:$reduce_or
-
-# Check that only one gate has a width of 5 and one gate has a width of 3
-select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
-select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain with branches for OR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
-  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_or
-
-# Check that both gates are 6 bits wide
-select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain with branches for OR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
-  assign x  = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_or
-
-# Check that only one gate has a width of 11 and one gate has a width of 6
-select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
-select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-###################################################################
-# Extract Reduce XOR Gates Tests
-###################################################################
-
-log -header "Simple XOR chain"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] a,
-  output wire x
-);
-  assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$xor
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "XOR chain with constants"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] a,
-  output wire x
-);
-  assign x = a[0] ^ a[1] ^ a[2] ^ 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$xor
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "XOR chain with multiple branches"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [5:0] a,
-  output wire x
-);
-  wire w0, w1, w2, w3;
-
-  assign w0 = a[0] ^ a[1];
-  assign w1 = a[2] ^ a[3];
-  assign w2 = a[4] ^ a[5];
-  assign w3 = w0 ^ w1;
-  assign x = w2 ^ w3;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates and inputs
-select -assert-count 0 t:$xor
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain XOR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] ^ a[1];
-  assign w1 = w0 ^ a[2];
-  assign w2 = w1 ^ a[3];
-  assign x = w2 ^ a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$xor
-select -assert-count 2 t:$reduce_xor
-
-# Check that both gates are 3 bits wide
-select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain for XOR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = a[0] ^ a[1];
-  assign w1 = w0 ^ a[2];
-  assign w2 = w1 ^ a[3];
-  assign x = w2 ^ a[4];
-
-  // Off-chain use of w1
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$xor
-select -assert-count 2 t:$reduce_xor
-
-# Check that only one gate has a width of 5 and one gate has a width of 3
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain with branches for XOR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
-  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$xor
-select -assert-count 2 t:$reduce_xor
-
-# Check that both gates are 6 bits wide
-select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
-
-design -reset
-log -pop
-
-
-
-log -header "Allow off-chain with branches for XOR"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [10:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0;
-
-  assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
-  assign x  = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
-
-  // Off-chain use of w0
-  assign y = w0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check final design has correct number of gates
-select -assert-count 0 t:$xor
-select -assert-count 2 t:$reduce_xor
-
-# Check that only one gate has a width of 11 and one gate has a width of 6
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
-select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
-
-design -reset
-log -pop
-
-###################################################################
-# Extract PMUX from MUX Chains Tests
-###################################################################
-
-log -header "Simple MUX chain to PMUX"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [2:0] sel,
-  input wire [3:0] a,
-  output wire x
-);
-  wire w0, w1;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : w0;
-  assign x  = sel[2] ? a[3] : w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got a single pmux with the correct input number
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "MUX chain with constants"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [2:0] sel,
-  input wire [2:0] a,
-  output wire x
-);
-  wire w0, w1;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : w0;
-  assign x  = sel[2] ? 1'b1 : w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got a single pmux with the correct input number
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "MUX chain with multiple branches"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [2:0] sel,
-  input wire [3:0] a,
-  output wire x
-);
-  wire w0, w1;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : a[3];
-  assign x  = sel[2] ? w0 : w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got a single pmux with the correct input number
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
-
-design -reset
-log -pop
-
-
-
-log -header "MUX chain with multiple uneven branches"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [5:0] sel,
-  input wire [6:0] a,
-  output wire x
-);
-  wire w0, w1, w2, w3, w4;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : w0;
-  assign w2 = sel[2] ? a[3] : w1;
-  assign w3 = sel[3] ? w2 : w4;
-  assign w4 = sel[5] ? a[4] : a[5];
-  assign x  = sel[4] ? w3 : a[6];
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got a single pmux with the correct input number
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux r:S_WIDTH=7 %i
-
-design -reset
-log -pop
-
-
-
-log -header "No off-chain MUX chain"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] sel,
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : w0;
-  assign w2 = sel[2] ? a[3] : w1;
-  assign x  = sel[3] ? a[4] : w2;
-
-  // Off-chain use of intermediate wire
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got two pmuxes
-select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-
-# Check that both pmuxes have input width of 3
-select -assert-none t:$pmux r:S_WIDTH!=3 %i
-
-design -reset
-log -pop
-
-
-
-
-log -header "Allow off-chain MUX chain"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire [3:0] sel,
-  input wire [4:0] a,
-  output wire x,
-  output wire y
-);
-  wire w0, w1, w2;
-
-  assign w0 = sel[0] ? a[1] : a[0];
-  assign w1 = sel[1] ? a[2] : w0;
-  assign w2 = sel[2] ? a[3] : w1;
-  assign x  = sel[3] ? a[4] : w2;
-
-  assign y = w1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after extract_reduce
-equiv_opt -assert extract_reduce -allow-off-chain
-
-# Load design and run opt_clean to remove unnecessary wires
-design -load postopt
-opt_clean
-
-# Check we got two $pmux
-select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-
-# Check that one pmux has an input width of 3 
-# and the other has an input width of 5
-select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
-select -assert-count 1 t:$pmux r:S_WIDTH=5 %i
-
-design -reset
-log -pop

From ba709dc0ed01d3035450d6b0a7db726e8fca0ae6 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Thu, 3 Apr 2025 10:37:32 -0700
Subject: [PATCH 09/10] added stress tests

---
 tests/silimate/extract_reduce_gates.ys | 116 +++++++++++++--
 tests/silimate/extract_reduce_muxes.ys | 188 ++++++++++++++++++++++---
 2 files changed, 268 insertions(+), 36 deletions(-)

diff --git a/tests/silimate/extract_reduce_gates.ys b/tests/silimate/extract_reduce_gates.ys
index c3a505651..c50db9bc7 100644
--- a/tests/silimate/extract_reduce_gates.ys
+++ b/tests/silimate/extract_reduce_gates.ys
@@ -824,29 +824,119 @@ log -pop
 
 
 
-# TODO
-log -header "Combinational feedback loop"
+log -header "Stress test"
 log -push
 design -reset
 read_verilog <<EOF
 module top (
-  input  wire a,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
   output wire y
 );
-  wire w0, w1;
+  wire c0, c1, c2;
 
-  // Two AND gates feeding each other
-  assign w0 = a & w1;
-  assign w1 = a & w0;
+  // Stage 0
+  wire s0_w0 = a0[0] & a0[1];
+  wire s0_w1 = a0[2] & a0[3];
+  wire s0_w2 = s0_w0 & s0_w1;
+  wire s0_w3 = s0_w2 & a0[4];
+  wire s0_w4 = a0[0] & a0[5];
+  wire s0_w5 = s0_w3 & a0[6];
+  wire s0_w6 = s0_w4 & a0[7];
+  assign c0 = s0_w5 & s0_w6;
 
-  assign y = w1;
+  // Stage 1
+  wire s1_w0 = a1[0] & a1[1];
+  wire s1_w1 = a1[2] & a1[3];
+  wire s1_w2 = s1_w0 & s1_w1;
+  wire s1_w3 = s1_w2 & a1[4];
+  wire s1_w4 = c0     & a1[5];
+  wire s1_w5 = s1_w3 & a1[6];
+  wire s1_w6 = s1_w4 & a1[7];
+  assign c1 = s1_w5 & s1_w6;
+
+  // Stage 2
+  wire s2_w0 = a2[0] & a2[1];
+  wire s2_w1 = a2[2] & a2[3];
+  wire s2_w2 = s2_w0 & s2_w1;
+  wire s2_w3 = s2_w2 & a2[4];
+  wire s2_w4 = c1     & a2[5];
+  wire s2_w5 = s2_w3 & a2[6];
+  wire s2_w6 = s2_w4 & a2[7];
+  assign c2 = s2_w5 & s2_w6;
+
+  assign y = c2;
 endmodule
 EOF
-# check -assert
+check -assert
 
 # Check equivalence after extract_reduce
-# equiv_opt -assert extract_reduce
-extract_reduce -allow-off-chain
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+extract_reduce
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test reconvergence"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire y
+);
+  wire c0, c1, c2;
+
+  // Stage 0
+  wire s0_w0 = a0[0] & a0[1];
+  wire s0_w1 = a0[2] & a0[3];
+  wire s0_w2 = s0_w0 & s0_w1;
+  wire s0_w3 = s0_w2 & a0[4];
+  wire s0_w4 = s0_w2 & a0[5];
+  wire s0_w5 = s0_w3 & a0[6];
+  wire s0_w6 = s0_w4 & a0[7];
+  assign c0 = s0_w5 & s0_w6;
+
+  // Stage 1
+  wire s1_w0 = a1[0] & a1[1];
+  wire s1_w1 = a1[2] & a1[3];
+  wire s1_w2 = s1_w0 & s1_w1;
+  wire s1_w3 = s1_w2 & a1[4];
+  wire s1_w4 = s1_w2 & a1[5];
+  wire s1_w5 = s1_w3 & a1[6];
+  wire s1_w6 = s1_w4 & c0;
+  assign c1 = s1_w5 & s1_w6;
+
+  // Stage 2
+  wire s2_w0 = a2[0] & a2[1];
+  wire s2_w1 = a2[2] & a2[3];
+  wire s2_w2 = s2_w0 & s2_w1;
+  wire s2_w3 = s2_w2 & a2[4];
+  wire s2_w4 = s2_w2 & a2[5];
+  wire s2_w5 = s2_w3 & a2[6];
+  wire s2_w6 = s2_w4 & c1;
+  assign c2 = s2_w5 & s2_w6;
+
+  assign y = c2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
 
 # Load design and run opt_clean to remove unnecessary wires
 design -load postopt
@@ -854,9 +944,7 @@ opt_clean
 
 # Check final design has correct number of gates and inputs
 select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
-select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+select -assert-count 4 t:$reduce_and
 
 design -reset
 log -pop
\ No newline at end of file
diff --git a/tests/silimate/extract_reduce_muxes.ys b/tests/silimate/extract_reduce_muxes.ys
index b5cd3b2a1..4950f1a6b 100644
--- a/tests/silimate/extract_reduce_muxes.ys
+++ b/tests/silimate/extract_reduce_muxes.ys
@@ -394,47 +394,191 @@ log -pop
 
 
 
-# TODO check about infinite loop
-log -header "Mux with feedback that causes infinite loop"
+log -header "Stress test"
 log -push
 design -reset
 read_verilog <<EOF
 module top (
-  input wire [2:0] sel,
-  input wire [3:0] a,
+  input  wire [5:0] sel0,
+  input  wire [5:0] sel1,
+  input  wire [5:0] sel2,
+  input  wire [6:0] a0,
+  input  wire [6:0] a1,
+  input  wire [6:0] a2,
   output wire x
 );
-  wire w0, w1;
+  wire x0, x1;
 
-  assign w0 = sel[0] ? a[0] : w0;
-  assign w1 = sel[1] ? a[1] : w0;
-  assign x  = sel[2] ? a[2] : w1;
+  // Stage 0
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? a0[3] : s0_w1;
+  wire s0_w4 = sel0[5] ? a0[4] : a0[5];
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w4;
+  assign x0  = sel0[4] ? s0_w3 : a0[6];
+
+  // Stage 1
+  wire s1_w0 = sel1[0] ? a1[1] : a1[0];
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? a1[3] : s1_w1;
+  wire s1_w4 = sel1[5] ? a1[4] : a1[5];
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w4;
+  assign x1  = sel1[4] ? s1_w3 : x0;
+
+  // Stage 2
+  wire s2_w0 = sel2[0] ? a2[1] : a2[0];
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? a2[3] : s2_w1;
+  wire s2_w4 = sel2[5] ? a2[4] : a2[5];
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w4;
+  assign x   = sel2[4] ? s2_w3 : x1;
 endmodule
 EOF
-# check -assert
-
-autoname
-write_json dump_pre.json
-exec -- netlistsvg dump_pre.json -o dump_pre.svg
+check -assert
 
 # Check equivalence after extract_reduce
-# equiv_opt -assert extract_reduce
-extract_reduce -allow-off-chain
+equiv_opt -assert extract_reduce
 
 # Load design and run opt_clean and opt_reduce to remove unnecessary cells
-# design -load postopt
+design -load postopt
 opt_clean
 opt_reduce
 
-autoname
-write_json dump_post.json
-exec -- netlistsvg dump_post.json -o dump_post.svg
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test with reconverging tree and no off chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] sel0,
+  input  wire [7:0] sel1,
+  input  wire [7:0] sel2,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire x
+);
+  wire x0, x1;
+
+  // Stage 0
+  wire s0_w6 = sel0[7] ? a0[7] : a0[4];
+  wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
+  wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
+  assign x0  = sel0[4] ? a0[6] : s0_w3;
+
+  // Stage 1
+  wire s1_w6 = sel1[7] ? a1[7] : a1[4];
+  wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
+  wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
+  wire s1_w0 = sel1[0] ? a1[1] : x0;
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
+  assign x1  = sel1[4] ? a1[6] : s1_w3;
+
+  // Stage 2
+  wire s2_w6 = sel2[7] ? a2[7] : a2[4];
+  wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
+  wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
+  wire s2_w0 = sel2[0] ? a2[1] : x1;
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
+  assign x   = sel2[4] ? a2[6] : s2_w3;
+endmodule
+
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
 
 # Check we got one pmux with correct number of inputs
 select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
-select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+select -assert-count 4 t:$pmux
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test with reconverging tree and yes off chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] sel0,
+  input  wire [7:0] sel1,
+  input  wire [7:0] sel2,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire x
+);
+  wire x0, x1;
+
+  // Stage 0
+  wire s0_w6 = sel0[7] ? a0[7] : a0[4];
+  wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
+  wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
+  assign x0  = sel0[4] ? a0[6] : s0_w3;
+
+  // Stage 1
+  wire s1_w6 = sel1[7] ? a1[7] : a1[4];
+  wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
+  wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
+  wire s1_w0 = sel1[0] ? a1[1] : x0;
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
+  assign x1  = sel1[4] ? a1[6] : s1_w3;
+
+  // Stage 2
+  wire s2_w6 = sel2[7] ? a2[7] : a2[4];
+  wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
+  wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
+  wire s2_w0 = sel2[0] ? a2[1] : x1;
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
+  assign x   = sel2[4] ? a2[6] : s2_w3;
+endmodule
+
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
 
 design -reset
 log -pop
\ No newline at end of file

From 05a3c28f39264721b97d9303d5a5206cea8d88e3 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Thu, 3 Apr 2025 10:38:55 -0700
Subject: [PATCH 10/10] small name change

---
 tests/silimate/extract_reduce_muxes.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/silimate/extract_reduce_muxes.ys b/tests/silimate/extract_reduce_muxes.ys
index 4950f1a6b..3f065b864 100644
--- a/tests/silimate/extract_reduce_muxes.ys
+++ b/tests/silimate/extract_reduce_muxes.ys
@@ -394,7 +394,7 @@ log -pop
 
 
 
-log -header "Stress test"
+log -header "Normal stress test"
 log -push
 design -reset
 read_verilog <<EOF