mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 11:25:53 +00:00
Code Activity

Wrap LUTRAMs in order to capture comb/seq behaviour

Browse source
This commit is contained in:
Eddie Hung 2019-08-20 14:49:11 -07:00
parent c00d72cdb3
commit 808f07630f
5 changed files with 200 additions and 36 deletions
Download patch file Download diff file Expand all files Collapse all files

64
techlibs/xilinx/abc_unmap.v
View file

@ -138,3 +138,67 @@ module \$__ABC_FDPE_1 (output Q,
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_LUTMUX (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
module \$__ABC_RAM32X1D (
output DPO, SPO,
input D,
input WCLK,
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
RAM32X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(DPO), .SPO(SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
endmodule
module \$__ABC_RAM64X1D (
output DPO, SPO,
input D,
input WCLK,
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
RAM64X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(DPO), .SPO(SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
endmodule
module \$__ABC_RAM128X1D (
output DPO, SPO,
input D,
input WCLK,
input WE,
input A,
input DPRA,
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
RAM128X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(DPO), .SPO(SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A(A),
.DPRA(DPRA)
);
endmodule