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Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass

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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2023-09-29 15:49:15 +02:00 • committed by Martin Povišer
parent 8bb70bac8d
commit 80119386c0
5 changed files with 238 additions and 13 deletions
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27
backends/rtlil/rtlil_backend.cc
View file

@ -118,13 +118,17 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
}
}
void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d)
{
for (auto &it : wire->attributes) {
f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
dump_const(f, it.second);
f << stringf("\n");
}
if (flag_d && wire->driverCell) {
f << stringf("%s" "driver %s %s\n", indent.c_str(),
wire->driverCell->name.c_str(), wire->driverPort.c_str());
}
f << stringf("%s" "wire ", indent.c_str());
if (wire->width != 1)
f << stringf("width %d ", wire->width);
@ -298,7 +302,7 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::
f << stringf("\n");
}
void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d)
{
bool print_header = flag_m || design->selected_whole_module(module->name);
bool print_body = !flag_n || !design->selected_whole_module(module->name);
@ -335,7 +339,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
if (!only_selected || design->selected(module, it)) {
if (only_selected)
f << stringf("\n");
dump_wire(f, indent + " ", it);
dump_wire(f, indent + " ", it, flag_d);
}
for (auto it : module->memories)
@ -384,7 +388,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
f << stringf("%s" "end\n", indent.c_str());
}
void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d)
{
int init_autoidx = autoidx;
@ -410,7 +414,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
if (!only_selected || design->selected(module)) {
if (only_selected)
f << stringf("\n");
dump_module(f, "", module, design, only_selected, flag_m, flag_n);
dump_module(f, "", module, design, only_selected, flag_m, flag_n, flag_d);
}
}
@ -456,7 +460,7 @@ struct RTLILBackend : public Backend {
log("Output filename: %s\n", filename.c_str());
*f << stringf("# Generated by %s\n", yosys_version_str);
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
RTLIL_BACKEND::dump_design(*f, design, selected, true, false, false);
}
} RTLILBackend;
@ -493,6 +497,9 @@ struct DumpPass : public Pass {
log(" -n\n");
log(" only dump the module headers if the entire module is selected\n");
log("\n");
log(" -d\n");
log(" include driver cell and port info on wires in dump format\n");
log("\n");
log(" -o <filename>\n");
log(" write to the specified file.\n");
log("\n");
@ -503,7 +510,7 @@ struct DumpPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool flag_m = false, flag_n = false, append = false;
bool flag_m = false, flag_n = false, flag_d = false, append = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -527,6 +534,10 @@ struct DumpPass : public Pass {
flag_n = true;
continue;
}
if (arg == "-d") {
flag_d = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -548,7 +559,7 @@ struct DumpPass : public Pass {
f = &buf;
}
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, flag_d);
if (!empty) {
delete f;

6
backends/rtlil/rtlil_backend.h
View file

@ -34,7 +34,7 @@ namespace RTLIL_BACKEND {
void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true);
void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true);
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true);
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d = false);
void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory);
void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell);
void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs);
@ -42,8 +42,8 @@ namespace RTLIL_BACKEND {
void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy);
void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc);
void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false);
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false);
}
YOSYS_NAMESPACE_END