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Added more help messages
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9 changed files with 121 additions and 11 deletions
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@ -298,7 +298,29 @@ static void autotest(FILE *f, RTLIL::Design *design)
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}
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struct AutotestBackend : public Backend {
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AutotestBackend() : Backend("autotest") { }
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AutotestBackend() : Backend("autotest", "generate simple test benches") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_autotest [filename]\n");
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log("\n");
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log("Automatically create primitive verilog test benches for all modules in the\n");
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log("design. The generated testbenches toggle the input pins of the module in\n");
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log("a semi-random manner and dumps the resulting output signals.\n");
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log("\n");
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log("This can be used to check the synthesis results for simple circuits by\n");
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log("comparing the testbench output for the input files and the synthesis results.\n");
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log("\n");
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log("The backend automatically detects clock signals. Additionally a signal can\n");
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log("be forced to be interpreted as clock signal by setting the attribute\n");
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log("'gentb_clock' on the signal.\n");
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log("\n");
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log("The attribute 'gentb_constant' can be used to force a signal to a constant\n");
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log("value after initialization. This can e.g. be used to force a reset signal\n");
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log("low in order to explore more inner states in a state machine.\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing AUTOTEST backend (auto-generate pseudo-random test benches).\n");
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