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fmt: remove lzero by lowering during Verilog parse

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See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
This commit is contained in:
Charlotte 2023-06-28 11:51:29 +10:00 • committed by Marcelina Kościelnicka
parent eb0fb4d662
commit 7f7c61c9f0
4 changed files with 82 additions and 41 deletions
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5
kernel/fmt.h
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@ -75,7 +75,6 @@ struct FmtPart {
// INTEGER type
unsigned base = 10;
bool signed_ = false;
bool lzero = false;
bool plus = false;
// TIME type
@ -83,6 +82,7 @@ struct FmtPart {
};
struct Fmt {
public:
std::vector<FmtPart> parts;
void append_string(const std::string &str);
@ -96,6 +96,9 @@ struct Fmt {
void emit_cxxrtl(std::ostream &f, std::function<void(const RTLIL::SigSpec &)> emit_sig) const;
std::string render() const;
private:
void apply_verilog_automatic_sizing_and_add(FmtPart &part);
};
YOSYS_NAMESPACE_END