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fmt: remove lzero by lowering during Verilog parse

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See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
This commit is contained in:
Charlotte 2023-06-28 11:51:29 +10:00 • committed by Marcelina Kościelnicka
parent eb0fb4d662
commit 7f7c61c9f0
4 changed files with 82 additions and 41 deletions
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7
backends/cxxrtl/cxxrtl.h
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@ -802,11 +802,10 @@ struct value_formatted {
int width;
int base;
bool signed_;
bool lzero;
bool plus;
value_formatted(const value<Bits> &val, bool character, bool justify_left, char padding, int width, int base, bool signed_, bool lzero, bool plus) :
val(val), character(character), justify_left(justify_left), padding(padding), width(width), base(base), signed_(signed_), lzero(lzero), plus(plus) {}
value_formatted(const value<Bits> &val, bool character, bool justify_left, char padding, int width, int base, bool signed_, bool plus) :
val(val), character(character), justify_left(justify_left), padding(padding), width(width), base(base), signed_(signed_), plus(plus) {}
value_formatted(const value_formatted<Bits> &) = delete;
value_formatted<Bits> &operator=(const value_formatted<Bits> &rhs) = delete;
};
@ -823,7 +822,7 @@ std::ostream &operator<<(std::ostream &os, const value_formatted<Bits> &vf)
if (!vf.character) {
size_t width = Bits;
if (!vf.lzero && vf.base != 10) {
if (vf.base != 10) {
width = 0;
for (size_t index = 0; index < Bits; index++)
if (val.bit(index))