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Added module->uniquify()

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This commit is contained in:
Clifford Wolf 2014-08-16 23:50:36 +02:00
parent f82c978e08
commit 7f734ecc09
5 changed files with 29 additions and 15 deletions
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5
passes/cmds/splitnets.cc
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@ -46,10 +46,7 @@ struct SplitnetsWorker
if (format.size() > 1)
new_wire_name += format.substr(1, 1);
while (module->count_id(new_wire_name) > 0)
new_wire_name += "_";
RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
new_wire->port_id = wire->port_id;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;

6
passes/fsm/fsm_map.cc
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@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
while (module->count_id(state_wire_name) > 0)
state_wire_name += "_";
RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");