mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-20 07:36:39 +00:00
Code Activity

test_cell: Update to $macc_v2

Browse source
This commit is contained in:
Martin Povišer 2025-04-17 10:53:13 +12:00 committed by Krystine Sherwin
parent 49eec407c2
commit 7f68a1ebd6
No known key found for this signature in database
1 changed files with 3 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
passes/tests/test_cell.cc
View file

@ -190,7 +190,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::CO, wire);
}
if (cell_type == ID($macc))
if (cell_type == ID($macc_v2))
{
Macc macc;
int width = 1 + xorshift32(8 * bloat_factor);
@ -224,6 +224,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
this_term.do_subtract = xorshift32(2) == 1;
macc.terms.push_back(this_term);
}
// Macc::to_cell sets the input ports
macc.to_cell(cell);
@ -231,12 +232,6 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
wire->width = width;
wire->port_output = true;
cell->setPort(ID::Y, wire);
// override the B input (macc helpers always sets an empty vector)
wire = module->addWire(ID::B);
wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
wire->port_input = true;
cell->setPort(ID::B, wire);
}
if (cell_type == ID($lut))
@ -1053,8 +1048,7 @@ struct TestCellPass : public Pass {
cell_types[ID($sop)] = "*";
cell_types[ID($alu)] = "ABSY";
cell_types[ID($lcu)] = "*";
// create_gold_module() needs updating for $macc_v2
// cell_types[ID($macc)] = "*";
cell_types[ID($macc_v2)] = "*";
cell_types[ID($fa)] = "*";
cell_types[ID($_BUF_)] = "AYb";