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Cleanup use of hard-coded default parameters in light of #1945
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db27f2f378
commit
7f33a0294b
9 changed files with 54 additions and 60 deletions
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@ -188,7 +188,7 @@ arg next
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// driven by the 'P' output of the previous DSP cell, and (c) has its
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// 'PCIN' port unused
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match nextP
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select !param(nextP, \CREG, State::S1).as_bool()
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select !param(nextP, \CREG).as_bool()
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select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011"))
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select nusers(port(nextP, \C, SigSpec())) > 1
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select nusers(port(nextP, \PCIN, SigSpec())) == 0
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@ -201,7 +201,7 @@ endmatch
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match nextP_shift17
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if !nextP
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select nextP_shift17->type.in(\DSP48E1)
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select !param(nextP_shift17, \CREG, State::S1).as_bool()
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select !param(nextP_shift17, \CREG).as_bool()
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select port(nextP_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP_shift17, \C, SigSpec())) > 1
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select nusers(port(nextP_shift17, \PCIN, SigSpec())) == 0
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@ -242,10 +242,10 @@ code argQ clock AREG
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if (next && next->type.in(\DSP48E1)) {
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Cell *prev = std::get<0>(chain.back());
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if (param(next, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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if (param(next, \A_INPUT).decode_string() == "DIRECT" &&
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port(next, \ACIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \ACOUT, SigSpec())) <= 1) {
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if (param(prev, \AREG, 2) == 0) {
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if (param(prev, \AREG) == 0) {
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if (port(prev, \A) == port(next, \A))
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AREG = 0;
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}
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@ -259,9 +259,9 @@ code argQ clock AREG
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTA, State::S0))
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goto reject_AREG;
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IdString CEA;
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if (param(prev, \AREG, 2) == 1)
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if (param(prev, \AREG) == 1)
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CEA = \CEA2;
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else if (param(prev, \AREG, 2) == 2)
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else if (param(prev, \AREG) == 2)
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CEA = \CEA1;
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else log_abort();
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if (!dffcemux && port(prev, CEA, State::S0) != State::S1)
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@ -282,11 +282,11 @@ code argQ clock BREG
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BREG = -1;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if (param(next, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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if ((next->type != \DSP48E1 || param(next, \B_INPUT).decode_string() == "DIRECT") &&
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port(next, \BCIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \BCOUT, SigSpec())) <= 1) {
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if ((next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG, 0) == 0 && param(prev, \B1REG, 1) == 0) ||
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(next->type.in(\DSP48E1) && param(prev, \BREG, 2) == 0)) {
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if ((next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) == 0 && param(prev, \B1REG) == 0) ||
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(next->type.in(\DSP48E1) && param(prev, \BREG) == 0)) {
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if (port(prev, \B) == port(next, \B))
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BREG = 0;
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}
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@ -303,9 +303,9 @@ code argQ clock BREG
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if (next->type.in(\DSP48A, \DSP48A1))
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CEB = \CEB;
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else if (next->type.in(\DSP48E1)) {
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if (param(prev, \BREG, 2) == 1)
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if (param(prev, \BREG) == 1)
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CEB = \CEB2;
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else if (param(prev, \BREG, 2) == 2)
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else if (param(prev, \BREG) == 2)
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CEB = \CEB1;
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else log_abort();
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}
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@ -315,7 +315,7 @@ code argQ clock BREG
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if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
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goto reject_BREG;
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if (dffD == unextend(port(prev, \B))) {
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if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG, 0) != 0)
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if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) != 0)
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goto reject_BREG;
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BREG = 1;
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}
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