mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
Added "read_verilog -nomeminit" and "nomeminit" attribute
This commit is contained in:
parent
a8e9d37c14
commit
7f1a1759d7
5 changed files with 34 additions and 7 deletions
|
@ -83,11 +83,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
|
|||
{
|
||||
AstNode *mem = it.first;
|
||||
uint32_t memflags = it.second;
|
||||
bool this_nomeminit = flag_nomeminit;
|
||||
log_assert((memflags & ~0x00ffff00) == 0);
|
||||
|
||||
if (mem->get_bool_attribute("\\nomem2reg"))
|
||||
continue;
|
||||
|
||||
if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit"))
|
||||
this_nomeminit = true;
|
||||
|
||||
if (memflags & AstNode::MEM2REG_FL_FORCED)
|
||||
goto silent_activate;
|
||||
|
||||
|
@ -97,7 +101,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
|
|||
if (memflags & AstNode::MEM2REG_FL_SET_ASYNC)
|
||||
goto verbose_activate;
|
||||
|
||||
if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE))
|
||||
if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE) && this_nomeminit)
|
||||
goto verbose_activate;
|
||||
|
||||
if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue