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Added "read_verilog -nomeminit" and "nomeminit" attribute

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Clifford Wolf 2015-02-14 11:21:12 +01:00
parent a8e9d37c14
commit 7f1a1759d7
5 changed files with 34 additions and 7 deletions
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@ -257,6 +257,11 @@ Verilog Attributes and non-standard features
- The "mem2reg" attribute on modules or arrays forces the early
conversion of arrays to separate registers.
- The "nomeminit" attribute on modules or arrays prohibits the
creation of initialized memories. This effectively puts "mem2reg"
on all memories that are written to in an "initial" block and
are not ROMs.
- The "nolatches" attribute on modules or always-blocks
prohibits the generation of logic-loops for latches. Instead
all not explicitly assigned values default to x-bits. This does