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QLF_TDP36K: more basic tdp/sdp sim tests

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Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
This commit is contained in:
Krystine Sherwin 2023-12-01 17:00:15 +13:00 • committed by Martin Povišer
parent 3d08ed216d
commit 7f12d0ba95
2 changed files with 90 additions and 5 deletions
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6
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
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@ -43,6 +43,7 @@ end
wire rce_a = rce_a_testvector[i];
wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i];
wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i];
wire [DATA_WIDTH-1:0] rq_a;
wire wce_a = wce_a_testvector[i];
@ -51,6 +52,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
wire rce_b = rce_b_testvector[i];
wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i];
wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i];
wire [DATA_WIDTH-1:0] rq_b;
wire wce_b = wce_b_testvector[i];
@ -63,9 +65,9 @@ always @(posedge clk) begin
if (i < VECTORLEN-1) begin
if (i > 0) begin
if($past(rce_a))
assert(rq_a == rq_a_expected[i]);
assert(rq_a == rq_a_e);
if($past(rce_b))
assert(rq_b == rq_b_expected[i]);
assert(rq_b == rq_b_e);
end
i <= i + 1;
end