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removed dump verilog

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William Zhu 2025-03-27 15:14:28 -07:00
parent 8666e9ae45
commit 7f04cc6755
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tests/silimate/mux_andnot.ys
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@ -215,7 +215,6 @@ equiv_opt -assert opt_expr -mux_bool
# Check final design has correct number of gates
design -load postopt
write_verilog dump.v
select -assert-count 1 t:$and
select -assert-count 1 t:$not