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More tests in memlib/generate.py

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Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
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37
tests/memlib/memlib_wren.txt Normal file
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ram block \RAM_WREN {
abits 4;
init none;
ifdef NO_BYTE {
# single enable signal
widths 4 8 global;
} else ifdef W4_B4 {
widths 4 global;
byte 4;
} else ifdef W8_B4 {
widths 8 global;
option "BYTESIZE" 4 {
byte 4;
}
} else ifdef W8_B8 {
width 8;
byte 8;
} else ifdef W16_B4 {
widths 16 global;
option "BYTESIZE" 4 {
byte 4;
}
} else ifdef W64_B8 {
widths 64 global;
option "BYTESIZE" 8 {
byte 8;
}
}
port srsw "A" {
clock posedge;
ifdef WRBE_SEPARATE {
wrbe_separate;
}
}
}