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More tests in memlib/generate.py

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Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
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19
tests/memlib/memlib_multilut.txt Normal file
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@ -0,0 +1,19 @@
ram distributed \LUT_MULTI {
abits 4;
width 2;
init any;
port arsw "RW" {
clock posedge;
}
ifdef PORTS_QUAD {
option "PORTS" "QUAD" {
port ar "R0" "R1" "R2" {
}
}
} else ifdef PORTS_OCT {
option "PORTS" "OCT" {
port ar "R0" "R1" "R2" "R3" "R4" "R5" "R6" {
}
}
}
}