mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00
Code Activity

More tests in memlib/generate.py

Browse source 
Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/memlib/memlib_lut.v
View file

@ -9,6 +9,7 @@ module RAM_LUT(
);
parameter INIT = 0;
parameter OPTION_INIT = "UNDEFINED";
parameter PORT_RW_CLK_POL = 1;
reg [3:0] mem [0:15];
@ -16,7 +17,13 @@ reg [3:0] mem [0:15];
integer i;
initial
for (i = 0; i < 16; i += 1)
mem[i] = INIT[i*4+:4];
case (OPTION_INIT)
"NONE": mem[i] = mem[i]; //?
"ZERO": mem[i] = 4'h0;
"ANY": mem[i] = INIT[i*4+:4];
"NO_UNDEF": mem[i] = INIT[i*4+:4];
"UNDEFINED": mem[i] = 4'hx;
endcase
assign PORT_R_RD_DATA = mem[PORT_R_ADDR];
assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR];