mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 20:17:55 +00:00
Code Activity

More tests in memlib/generate.py

Browse source 
Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

18
tests/memlib/memlib_lut.txt
View file

@ -1,7 +1,23 @@
ram distributed \RAM_LUT {
abits 4;
width 4;
init any;
ifdef INIT_NONE {
option "INIT" "NONE" {
init none;
}
} else ifdef INIT_ZERO {
option "INIT" "ZERO" {
init zero;
}
} else ifdef INIT_NO_UNDEF {
option "INIT" "NO_UNDEF" {
init no_undef;
}
} else {
option "INIT" "ANY" {
init any;
}
}
cost 4;
port ar "R" {
}