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More tests in memlib/generate.py

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Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
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76
tests/memlib/memlib_clock_sdp.txt Normal file
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ram block \RAM_CLOCK_SDP {
cost 64;
abits 10;
widths 1 2 4 8 16 per_port;
init any;
port sw "W" {
ifdef SHARED_CLK {
ifdef WCLK_ANY {
option "WCLK" "ANY" {
clock anyedge "CLK";
}
}
ifdef WCLK_POS {
option "WCLK" "POS" {
clock posedge "CLK";
}
}
ifdef WCLK_NEG {
option "WCLK" "NEG" {
clock negedge "CLK";
}
}
} else {
ifdef WCLK_ANY {
option "WCLK" "ANY" {
clock anyedge;
}
}
ifdef WCLK_POS {
option "WCLK" "POS" {
clock posedge;
}
}
ifdef WCLK_NEG {
option "WCLK" "NEG" {
clock negedge;
}
}
}
}
port sr "R" {
ifdef SHARED_CLK {
ifdef RCLK_ANY {
option "RCLK" "ANY" {
clock anyedge "CLK";
}
}
ifdef RCLK_POS {
option "RCLK" "POS" {
clock posedge "CLK";
}
}
ifdef RCLK_NEG {
option "RCLK" "NEG" {
clock negedge "CLK";
}
}
} else {
ifdef RCLK_ANY {
option "RCLK" "ANY" {
clock anyedge;
}
}
ifdef RCLK_POS {
option "RCLK" "POS" {
clock posedge;
}
}
ifdef RCLK_NEG {
option "RCLK" "NEG" {
clock negedge;
}
}
}
}
}